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82551ER Fast Ethernet PCI Controller
Networking Silicon - 82551ER
Datasheet
Product Features
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Enhanced IP Protocol Support -- TCP, UDP, IPv4 Checksum Offload -- Received Checksum Verification Quality of Service (QoS) -- Multiple Priority Transmit Queues Optimum Integration for Lowest Cost Solution -- Integrated IEEE 802.3 10BASE-T and 100BASE-TX compatible PHY -- 32-bit PCI master interface -- Thin BGA 15mm2 package Integrated power management functions -- ACPI and PCI Power Management standards compliance -- Wake on "interesting" packets and link status change support
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High Performance Networking Functions -- Early release -- 8255x controller family chained memory structure -- Improved dynamic transmit chaining with multiple priorities transmit queues -- Full pin compatibility with the 82559 and 82559ER controllers -- Backward compatible software to 82559ER controller -- Full Duplex support at 10 and 100 Mbps -- IEEE 802.3u Auto-Negotiation support -- 3 Kbyte transmit and receive FIFOs -- Fast back-to-back transmission support with minimum interframe spacing -- IEEE 802.3x 100BASE-TX Flow Control support -- Adaptive Technology Low Power Features -- Advanced Power Management capabilities -- Low power 3.3 V device -- Efficient dynamic standby mode -- Deep power down support -- Clockrun protocol support 82551ER Enhancements -- Improved Bit Error Rate performance -- HWI support -- Deep Power-down state power reduction
Revision 2.1 March 2003
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 82551ER may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's Web site at http://www.intel.com. Copyright (c) 2003, Intel Corporation. * Other product and corporate names may be trademarks of other companies and are used only for explanation and to the owners' benefit, without intent to infringe.
Datasheet
Networking Silicon -- 82551ER
Revision History
Revision Date Nov 2001 Jan 2002 Revision 0.7 1.0 Description Initial draft for release (Intel Secret). * * * * Added description for No Connect pins. Clarified EEPROM address map and word definitions for the 82551ER. Added more detailed information for ICC in the DC specifications table. Corrected typographical errors.
Apr 2002 Mar 2003
2.0 2.1
Changed document status to Intel Confidential. * Removed document status. * Removed references to MDI/MDI-X feature, which is not supported by the 82551ER.
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Contents
1.0 Introduction......................................................................................................................... 1 1.1 1.2 1.3 1.4 2.0 Overview ............................................................................................................... 1 Byte Ordering ........................................................................................................ 1 References ............................................................................................................ 1 Product Codes....................................................................................................... 1
Architectural Overview ....................................................................................................... 3 2.1 2.2 2.3 2.4 Parallel Subsystem Overview................................................................................3 FIFO Subsystem Overview ................................................................................... 3 10/100 Mbps Serial CSMA/CD Unit Overview ......................................................4 10/100 Mbps Physical Layer Unit.......................................................................... 4
3.0
Performance Enhancements..............................................................................................5 3.1 3.2 3.3 Multiple Priority Transmit Queues .........................................................................5 Early Release ........................................................................................................ 5 Hardware Integrity Support ................................................................................... 6
4.0
Signal Descriptions............................................................................................................. 7 4.1 4.2 Signal Type Definitions ......................................................................................... 7 PCI Bus Interface Signals ..................................................................................... 8 4.2.1 Address and Data Signals ....................................................................... 8 4.2.2 Interface Control Signals .........................................................................8 4.2.3 System and Power Management Signals ...............................................9 Local Memory Interface Signals .......................................................................... 10 Test Port Signals ................................................................................................ 11 PHY Signals ....................................................................................................... 12 Power and Ground Signals ................................................................................. 13
4.3 4.4 4.5 4.6 5.0
Media Access Control Functional Description ..................................................................15 5.1 5.2 Device Initialization.............................................................................................. 15 5.1.1 Initialization Effects................................................................................. 15 PCI Interface ....................................................................................................... 16 5.2.1 Bus Operations....................................................................................... 16 5.2.2 Clockrun Signal ...................................................................................... 24 5.2.3 Power Management Event ..................................................................... 25 PCI Power Management .....................................................................................25 5.3.1 Power States ..........................................................................................25 5.3.2 Wake-up Events .....................................................................................29 Parallel Flash....................................................................................................... 30 Serial EEPROM Interface.................................................................................... 30 10/100 Mbps CSMA/CD Unit............................................................................... 33 5.6.1 Full Duplex ............................................................................................. 33 5.6.2 Flow Control ........................................................................................... 33 5.6.3 Address Filtering Modifications .............................................................. 33 5.6.4 Long Frame Reception ........................................................................... 34 Media Independent Interface (MII) Management Interface .................................34
5.3
5.4 5.5 5.6
5.7
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6.0
Physical Layer Functional Description ............................................................................. 35 6.1 100BASE-TX PHY Unit ....................................................................................... 35 6.1.1 100BASE-TX Transmit Clock Generation .............................................. 35 6.1.2 100BASE-TX Transmit Blocks ............................................................... 35 6.1.3 100BASE-TX Receive Blocks ................................................................ 35 6.1.4 100BASE-TX Link Integrity Auto-Negotiation......................................... 36 10BASE-T PHY Functions .................................................................................. 36 6.2.1 10BASE-T Transmit Clock Generation................................................... 36 6.2.2 10BASE-T Transmit Blocks.................................................................... 36 6.2.3 10BASE-T Receive Blocks..................................................................... 36 6.2.4 10BASE-T Link Integrity and Full Duplex ............................................... 37 Auto-Negotiation ................................................................................................. 37 6.3.1 Description ............................................................................................. 37 6.3.2 Parallel Detect and Auto-Negotiation ..................................................... 37 LED Description .................................................................................................. 38
6.2
6.3
6.4 7.0
Configuration Registers.................................................................................................... 41 7.1 LAN (Ethernet) PCI Configuration Space............................................................ 41 7.1.1 PCI Vendor ID and Device ID Registers ................................................ 41 7.1.2 PCI Command Register ......................................................................... 42 7.1.3 PCI Status Register................................................................................ 43 7.1.4 PCI Revision ID Register........................................................................ 44 7.1.5 PCI Class Code Register ....................................................................... 44 7.1.6 PCI Cache Line Size Register................................................................ 44 7.1.7 PCI Latency Timer ................................................................................. 45 7.1.8 PCI Header Type ................................................................................... 45 7.1.9 PCI Base Address Registers.................................................................. 45 7.1.10 Base Address Registry Summary .......................................................... 47 7.1.11 PCI Subsystem Vendor ID and Subsystem ID Registers....................... 47 7.1.12 Capability Pointer ................................................................................... 48 7.1.13 Interrupt Line Register............................................................................ 48 7.1.14 Interrupt Pin Register ............................................................................. 48 7.1.15 Minimum Grant Register ........................................................................ 48 7.1.16 Maximum Latency Register.................................................................... 48 7.1.17 Capability ID Register ............................................................................ 48 7.1.18 Next Item Pointer ................................................................................... 48 7.1.19 Power Management Capabilities Register ............................................. 49 7.1.20 Power Management Control/Status Register (PMCSR)......................... 49 7.1.21 Data Register ......................................................................................... 50
8.0
Control/Status Registers .................................................................................................. 51 8.1 LAN (Ethernet) Control/Status Registers ............................................................ 51 8.1.1 System Control Block Status Word ........................................................ 52 8.1.2 System Control Block Command Word.................................................. 53 8.1.3 System Control Block General Pointer................................................... 53 8.1.4 PORT ..................................................................................................... 53 8.1.5 Flash Control Register ........................................................................... 53 8.1.6 EEPROM Control Register..................................................................... 54 8.1.7 Management Data Interface Control Register........................................ 54 8.1.8 Receive Direct Memory Access Byte Count........................................... 54
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8.2 9.0
8.1.9 Flow Control Register ............................................................................. 54 8.1.10 General Control Register........................................................................ 55 8.1.11 General Status Register .........................................................................55 Statistical Counters ............................................................................................. 55
PHY Unit Registers .......................................................................................................... 59 9.1 MDI Registers 0 - 7 ............................................................................................. 59 9.1.1 Register 0: Control Register ..................................................................59 9.1.2 Register 1: Status Register ................................................................... 60 9.1.3 Register 2: PHY Identifier Register ....................................................... 61 9.1.4 Register 3: PHY Identifier Register ....................................................... 61 9.1.5 Register 4: Auto-Negotiation Advertisement Register ........................... 61 9.1.6 Register 5: Auto-Negotiation Link Partner Ability Register .................... 62 9.1.7 Register 6: Auto-Negotiation Expansion Register .................................62 MDI Registers 8 - 15 ........................................................................................... 62 MDI Register 16 - 31 ........................................................................................... 63 9.3.1 Register 16: PHY Unit Status and Control Register .............................. 63 9.3.2 Register 17: PHY Unit Special Control Register ................................... 63 9.3.3 Register 18: PHY Address Register ....................................................... 64 9.3.4 Register 19: 100BASE-TX Receive False Carrier Counter ...................64 9.3.5 Register 20: 100BASE-TX Receive Disconnect Counter ...................... 65 9.3.6 Register 21: 100BASE-TX Receive Error Frame Counter .................... 65 9.3.7 Register 22: Receive Symbol Error Counter ......................................... 65 9.3.8 Register 23: 100BASE-TX Receive Premature End of Frame Error Counter 65 9.3.9 Register 24: 10BASE-T Receive End of Frame Error Counter ............. 65 9.3.10 Register 25: 10BASE-T Transmit Jabber Detect Counter .....................66 9.3.11 Register 26: Equalizer Control and Status Register .............................. 66 9.3.12 Register 27: PHY Unit Special Control Register ................................... 66 9.3.13 Register 28: Reserved............................................................................ 66 9.3.14 Register 29: Hardware Integrity Control Register .................................. 67
9.2 9.3
10.0
Electrical and Timing Specifications................................................................................. 69 10.1 10.2 10.3 10.4 Absolute Maximum Ratings................................................................................. 69 DC Specifications ............................................................................................... 69 AC Specifications ................................................................................................ 73 Timing Specifications ..........................................................................................74 10.4.1 Clocks Specifications ............................................................................. 74 10.4.2 Timing Parameters ................................................................................. 75
11.0
Package and Pinout Information ...................................................................................... 83 11.1 11.2 Package Information ........................................................................................... 83 Pinout Information ............................................................................................... 84 11.2.1 Pin Assignments .................................................................................... 84 11.2.2 Ball Grid Array Diagram .........................................................................86
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1.0
Introduction
This datasheet is applicable to the Intel(R) 82551ER Fast Ethernet PCI Controller, a member of the 8255x Fast Ethernet Controller family.
1.1
Overview
The 82551ER is an evolutionary addition to Intel's family of 8255x controllers. It provides excellent performance by offloading TCP, UDP and IP checksums and supports TCP segmentation off-load. Its optimized 32-bit interface and efficient scatter-gather bus mastering capabilities enable the 82551ER to perform high speed data transfers over the PCI bus. This capability accelerates the processing of high level commands and operations, which lowers CPU utilization. Its architecture enables data to flow efficiently from the bus interface unit to the 3 Kbyte Transmit and Receive FIFOs, providing the perfect balance between the wire and system bus. In addition, multiple priority queues are provided to prevent data underruns and overruns. The 82551ER includes both a MAC and PHY. In also has a simple interface to the analog front end, which allows cost effective designs requiring minimal board real estate. The 82551ER is pin compatible with the 82550 and 82559 family of controllers and is offered with software that provides backwards compatibility with previous 8255x controllers.
1.2
Byte Ordering
TCP and IP Internet Engineering Task Force (IETF) Request for Comments (RFCs) and literature use big endian (BE) byte ordering. This document uses big endian ordering for all IP and TCP frame formats. However, little endian byte ordering is used for referencing 82551ER memory resident structures and internal structures.
1.3
References
The following documents may provide further information on topics discussed in this document.
* 10/100 Mbit Ethernet Controller Family Software Developer's Manual. Intel Corporation. * Advanced Configuration and Power Interface Specification, Revision 1.0. Intel Corporation,
Microsoft Corporation, and Toshiba.
* IEEE 802.3x and 802.1y Standards. * Network Device Class Power Management Reference Specification, Revision 1.0a. AMD, Inc.
and Microsoft Corporation.
1.4
Product Codes
The product ordering code for the 82551ER is: GD82551ER.
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2.0
Architectural Overview
The Intel(R) 82551ER is divided into four main subsystems: a parallel subsystem, a FIFO subsystem, a 10/100 Mbps Carrier Sense Multiple Access with Collision Detect (CSMA/CD) unit, and a 10/ 100 Mbps physical layer (PHY) unit.
2.1
Parallel Subsystem Overview
The parallel subsystem is comprised of several functional blocks: a PCI bus master interface, a micromachine processing unit and its corresponding microcode ROM, and a PCI Target Control/ Flash/EEPROM interface. The parallel subsystem also interfaces to the FIFO subsystem, passing data (such as transmit, receive, and configuration data) and command and status parameters between these two blocks. The PCI bus master interface provides a complete glueless interface to a PCI bus and is compliant with the PCI Bus Specification, Revision 2.2. The 82551ER provides 32 bits of addressing and data, as well as the PCI control interface. As a PCI target, it conforms to the PCI configuration scheme, which allows all accesses to the 82551ER to be automatically mapped into free memory and I/O space upon initialization of a PCI system. When transmit and receive data is processed, the 82551ER operates as a master on the PCI bus, initiating zero wait state transfers. The 82551ER Control/Status Register Block is part of the PCI target element. The Control/Status Register block consists of the following 82551ER internal control registers: System Control Block (SCB), PORT, Flash Control, EEPROM Control, and Management Data Interface (MDI) Control. An embedded micromachine consisting of independent transmit and receive processing units allow the 82551ER to execute commands and receive incoming frames with no real time CPU intervention. The 82551ER contains a multiplexed interface to connect an external serial EEPROM and Flash memory. The Flash interface, which can also be used to connect to any standard 8-bit device, provides up to 128 Kbyte of addressing to the Flash. Both read and write accesses are supported. The Flash can be used for remote boot functions, network statistical and diagnostics functions, and management functions. The Flash is mapped into host system memory (anywhere within the 32-bit memory address space) for software accesses. It is also mapped into an available boot expansion ROM location during boot time of the system. More information on the Flash interface is detailed in Section 5.4, "Parallel Flash". The serial EEPROM is used to store relevant information for a LAN connection such as node address, as well as board manufacturing and configuration information. Both read and write accesses to the EEPROM are supported by the 82551ER. Information on the EEPROM interface is detailed in Section 5.5, "Serial EEPROM Interface".
2.2
FIFO Subsystem Overview
The 82551ER FIFO subsystem consists of independent 3 Kbyte transmit and receive FIFOs. Each FIFO provides a temporary buffer for frames as they are transmitted or received. Transmit frames queued within the transmit FIFO allow back-to-back transmission within the minimum Interframe Spacing (IFS). The FIFOs allow the 82551ER to withstand long PCI bus latencies without losing incoming data. Additional attributes of the FIFOs that enhance performance and functionality are:
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* Tunable transmit FIFO threshold allows elimination of underruns while concurrent transmits
are being performed.
* Extended PCI zero wait state burst accesses to and from the 82551ER for both transmit and
receive FIFOs
* Efficient re-transmission of data directly from the transmit FIFO when physical or data link
errors (collision detection or data underrun) are encountered, increasing performance by eliminating the need to re-access the data from host memory
* Automatic discard of incoming runt receive frames
The 82551ER FIFO Subsystem consists of independent 3 Kbyte transmit and receive FIFOs. Each FIFO provides a temporary buffer for frames as they are received or transmitted. Transmit frames queued within the transmit FIFO allow back-to-back transmission within the minimum Interframe Spacing (IFS). The FIFOs allow the 82551ER to withstand long PCI bus latencies without losing incoming data. Additional attributes of the FIFOs that enhance performance and functionality are:
2.3
10/100 Mbps Serial CSMA/CD Unit Overview
The 82551ER's CSMA/CD unit allows it to be connected to a 10 or 100 Mbps Ethernet network at half or full duplex. The CSMA/CD unit performs all of the functions of the 802.3 protocol such as frame formatting, frame stripping, collision handling, deferral to link traffic, etc.
2.4
10/100 Mbps Physical Layer Unit
The integrated Physical Layer (PHY) unit of the 82551ER allows connection to either a 10 or 100 Mbps Ethernet network. The PHY supports Auto-Negotiation for 100BASE-TX Full Duplex, 100BASE-TX Half Duplex, 10BASE-T Full Duplex, and 10BASE-T Half Duplex. Three LED pins indicate link status, network activity, and speed.
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Networking Silicon -- 82551ER
3.0
Performance Enhancements
All of Intel's Fast Ethernet controllers have the ability to support full wire speeds. The 82551ER has been designed to provide improved networking throughput. Performance is limited to the system's ability to feed data to the network controller. As networks grow, the task of servicing the network becomes a large burden on the platform. System bottlenecks prevent optimal performance in typical operating conditions. Thus, to help alleviate these issues, Network Operating System (NOS) vendors are establishing normalized offload specifications. These specifications define the types of off-load support required by the OS and interface between the network drivers. The 82551ER provides support for these initiatives and enables an improvement in platform network efficiency. With the pervasiveness of Internet Protocols, the off-load capabilities have focused on improving IP efficiency. As part of this effort, the 82551ER includes support for Multiple Priority Transmit Queues.
3.1
Multiple Priority Transmit Queues
The 82551ER supports two queues: High Priority Queue (HPQ) and Low Priority Queue (LPQ). The 82551ER provides a method for the driver to modify the HPQ while processing data. A new read only register is defined in the Control/Status Register (CSR) that enables the driver to change the transmit priority of elements within the HPQ. When software reads this register, the address of the next Command Block to be processed by the 82551ER on the HPQ is returned. After reading this register, software can freely modify the next Command Block (for example, overwrite it with a different Command Block) and any subsequent Command Block, without any conflict with the 82551ER. Note: The Command Block Pointer register (in the CSR) is only active when the device is in the enhanced 82551ER mode.
3.2
Early Release
Like the 82558, 82559 and 82559ER, the 82551ER supports a 3Kbyte transmit FIFO. The 82551ER provides a transmit FIFO enhancement called "early release" that effectively increases the amount of free capacity in the transmit FIFO. The enabling of early release is controlled through configuration space and occurs when the following conditions are met: 1. The transmitted frame is the oldest one in the queue (in other words, it is located at the head of the queue). 2. The transmitted frame has been completely transferred to the XMT-SRAM and processed (for example, XSUM). Large frames (greater than 3 Kbyte) are never candidates for an early release. 3. When the preemptive queue mechanism is on, a frame which satisfies condition 2 may not satisfy condition 1 and therefore will not benefit from an early release. 4. More than 128 bytes have already been transferred to the XMT-SYNC-FIFO. This condition guarantees that at least one slot time elapsed (collision window).
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3.3
Hardware Integrity Support
Cabling problems are a common cause for network downtime situations. Hardware Integrity (HWI) can help reduce this by locating cabling problems. It uses transmission line theory to measure the arrival time and electrical characteristics of the wave reflected from an incident test wave launched on the media. With these measurements, opens, shorts, and degraded cable quality can be located along the wire. HWI is controlled and activated by software. The Hardware Integrity Control, register 29 of the MDI Registers, is used for activating HWI (Section 11.3.14, "Register 29: Hardware Integrity Control").
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Networking Silicon -- 82551ER
4.0
4.1
Table 1.
Signal Descriptions
Signal Type Definitions
Signal Type Descriptions
Type IN OUT TS Input Output Tri-State Name Description The input pin is a standard input only signal. The output pin is a Totem Pole Output pin and is a standard active driver. The tri-state pin is a bidirectional, input/output pin. The sustained tri-state pin is an active low tri-state signal owned and driven by one agent at a time. The agent asserting the STS pin low must drive it high at least one clock cycle before floating the pin. A new agent can only assert an STS signal low one clock cycle after it has been tri-stated by the previous owner. The open drain pin allows multiple devices to share this signal as a wired-OR. The analog input pin is used for analog input signals. The analog output pin is used for analog output signals. The bias pin is an input bias.
STS
Sustained Tri-State
OD AI AO B DPS APS
Open Drain Analog Input Analog Output Bias
Digital Power Supply Digital power or ground for the device. Analog Power Supply Analog power or ground for the device.
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4.2
4.2.1
Table 2.
PCI Bus Interface Signals
Address and Data Signals
Address and Data Signals
Symbol Type Name and Function Address and Data. The address and data lines are multiplexed on the same PCI pins. A bus transaction consists of an address phase followed by one or more data phases. During the address phase, the address and data lines contain the 32-bit physical address. For I/O, this is a byte address; for configuration and memory, it is a Dword address. The 82551ER uses little-endian byte ordering (in other words, AD[31:24] contain the most significant byte and AD[7:0] contain the least significant byte). During the data phases, the address and data lines contain data. Command and Byte Enable. The bus command and byte enable signals are multiplexed on the same PCI pins. During the address phase, the C/BE# lines define the bus command. During the data phase, the C/BE# lines are used as Byte Enables. The Byte Enables are valid for the entire data phase and determine which byte lanes carry meaningful data. Parity. Parity is even across AD[31:0] and C/BE[3:0]# lines. It is stable and valid one clock after the address phase. For data phases, PAR is stable and valid one clock after either IRDY# is asserted on a write transaction or TRDY# is asserted on a read transaction.Once PAR is valid, it remains valid until one clock after the completion of the current data phase. The master drives PAR for address and write data phases; and the target, for read data phases.
AD[31:0]
TS
C/BE[3:0]#
TS
PAR
TS
4.2.2
Table 3.
Interface Control Signals
Interface Control Signals
Symbol Type Name and Function Cycle Frame. The cycle frame signal is driven by the current master to indicate the beginning and duration of a transaction. FRAME# is asserted to indicate the start of a transaction and de-asserted during the final data phase. Initiator Ready. The initiator ready signal indicates the bus master's ability to complete the current data phase and is used in conjunction with the target ready (TRDY#) signal. A data phase is completed on any clock cycle where both IRDY# and TRDY# are sampled asserted (low) simultaneously. Target Ready. The target ready signal indicates the selected device's ability to complete the current data phase and is used in conjunction with the initiator ready (IRDY#) signal. A data phase is completed on any clock cycle where both IRDY# and TRDY# are sampled asserted (low) simultaneously. Stop. The stop signal is driven by the target to indicate to the initiator that it wishes to stop the current transaction. As a bus slave, STOP# is driven by the 82551ER to inform the bus master to stop the current transaction. As a bus master, STOP# is received by the 82551ER to stop the current transaction.
FRAME#
STS
IRDY#
STS
TRDY#
STS
STOP#
STS
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Networking Silicon -- 82551ER
Table 3.
Interface Control Signals
Symbol Type Name and Function Initialization Device Select. The initialization device select signal is used by the 82551ER as a chip select during PCI configuration read and write transactions. This signal is provided by the host in PCI systems. Device Select. The device select signal is asserted by the target once it has detected its address. As a bus master, the DEVSEL# is an input signal to the 82551ER indicating whether any device on the bus has been selected. As a bus slave, the 82551ER asserts DEVSEL# to indicate that it has decoded its address as the target of the current transaction. Request. The request signal indicates to the bus arbiter that the 82551ER desires use of the bus. This is a point-to-point signal and every bus master has its own REQ#. Grant. The grant signal is asserted by the bus arbiter and indicates to the 82551ER that access to the bus has been granted. This is a pointto-point signal and every master has its own GNT#. Interrupt A. The interrupt A signal is used to request an interrupt by the 82551ER. This is an active low, level-triggered interrupt signal. System Error. The system error signal is used to report address parity errors. When an error is detected, SERR# is driven low for a single PCI clock. Parity Error. The parity error signal is used to report data parity errors during all PCI transactions except a Special Cycle. The parity error pin is asserted two clock cycles after the error was detected by the device receiving data. The minimum duration of PERR# is one clock for each data phase where an error is detected. A device cannot report a parity error until it has claimed the access by asserting DEVSEL# and completed a data phase.
IDSEL
IN
DEVSEL#
STS
REQ#
TS
GNT#
IN
INTA#
OD
SERR#
OD
PERR#
STS
4.2.3
Table 4.
System and Power Management Signals
System and Power Management Signals
Symbol Type Name and Function Clock. The Clock signal provides the timing for all PCI transactions and is an input signal to every PCI device. The 82551ER requires a PCI Clock signal (frequency greater than or equal to 16 MHz) for nominal operation. The 82551ER supports Clock signal suspension using the Clockrun protocol. Clockrun. The Clockrun signal is used by the system to pause or slow down the PCI Clock signal. It is used by the 82551ER to enable or disable suspension of the PCI Clock signal or restart of the PCI clock. When the Clockrun signal is not used, this pin should be connected to an external pull-down resistor. Reset. The PCI Reset pin is used to place PCI registers, sequencers, and signals into a consistent state. When RST# is asserted, the 82551ER ignores other PCI signals and all PCI output signals will be tristated. The PCI Reset pin should be pulled high to the main digital power supply. Power Management Event. The Power Management Event signal indicates that a power management event has occurred in a PCI bus system.
CLK
IN
CLKRUN#
IN/OUT OD
RST#
IN
PME#
OD
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Table 4.
System and Power Management Signals
Symbol Type Name and Function Isolate. The Isolate pin is used to isolate the 82551ER from the PCI bus. It also provides PCI Reset pin functionality. When Isolate is active (low), the 82551ER does not drive its PCI outputs (except PME# and CSTSCHG) or sample its PCI inputs (including CLK and RST#). The ISOLATE# pin should be driven by the PCI Reset signal. Alternate Reset. The Alternate Reset pin is used to reset the 82551ER on power-up. The Alternate Reset signal should be pulled high to the main digital power supply. Voltage Input/Output. The VIO pin is the voltage bias pin and should be connected to a 5 V supply in a 5 V PCI signaling environment and a 3.3 V supply in 3.3 V signaling environment.
ISOLATE#
IN
ALTRST#
IN B IN
VIO
4.3
Note:
Local Memory Interface Signals
All unused Flash Address and Data pins MUST be left floating. Some of these pins have undocumented test functionality and can cause unpredictable behavior if they are unnecessarily connected to a pull-up or pull-down resistor. Local Memory Interface Signals
Symbol FLD[7:0] Type IN/OUT Name and Function Flash Data Input/Output. These pins are used for Flash data interface. These pins should be left floating if the Flash is not used. Flash Address[16]/25 MHz Clock. This multiplexed pin is controlled by the status of the Flash Address[7] (FLA[7]) pin. If FLA[7] is left floating, this pin is used as FLA[16]; otherwise, if FLA[7] is connected to a pull-up resistor, this pin is used as a 25 MHz clock output. This pin should be left floating if the Flash and the CLK25 functionality are not used. Flash Address[15]/EEPROM Data Output. During Flash accesses, this multiplexed pin acts as the Flash Address [15] output signal. During EEPROM accesses, it acts as the serial shift clock output to the EEPROM. Flash Address[14]/EEPROM Data Output. During Flash accesses, this multiplexed pin acts as the Flash Address [14] output signal. During EEPROM accesses, this pin accepts serial input data from the EEPROM Data Output pin. Flash Address[13]/EEPROM Data Input. During Flash accesses, this multiplexed pin acts as the Flash Address [13] output signal. During EEPROM accesses, this pin provides serial output data to the EEPROM Data Input pin. Flash Address[12:8]. These pins act as Flash address outputs. They should be left floating if Flash is not used. Flash Address[7]/Clock Enable. This multiplexed pin acts as the Flash Address[7] output signal during nominal operation. When the power-on reset of the 82551ER is active, this pin acts as input control over the FLA[16]/CLK25 output signal. If the FLA[7]/CLKEN pin is connected to a pull-up resistor (3.3 K), a 25 MHz clock signal is provided on the FLA[16]/CLK25 output; otherwise, it is used as FLA[16] output. For systems that do not use the 25 MHz clock output or Flash, this pin should be left floating.
Table 5.
FLA[16]/ CLK25
IN/OUT
FLA[15]/ EESK
IN/OUT
FLA[14]/ EEDO
IN/OUT
FLA[13]/ EEDI
IN/OUT
FLA[12:8]
OUT
FLA[7]/ CLKEN
IN/OUT
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Table 5.
Local Memory Interface Signals
Symbol FLA[6:2] Type OUT Name and Function Flash Address[6:2]. These pins are used as Flash address outputs. These pins should be left floating if the Flash is not used. Flash Address[1]/Auxiliary Power. This multiplexed pin acts as the Flash Address[1] output signal during nominal operation. When the power-on reset of the 82551ER is active (low), it acts as the power supply indicator. If the 82551ER is fed by auxiliary power, it should be connected to VCC through a pull-up resistor (3.3 K). Otherwise, this pin should be left floating. Flash Address [0]/PCI Mode. This multiplexed pin acts as the Flash Address[0] output signal during nominal operation. When power-on reset of the 82551ER is active (low), it acts as the input system type. For PCI systems that do not use Flash, this pin should be left floating. EEPROM Chip Select. The EEPROM Chip Select signal is used to assert chip select to the serial EEPROM. Flash Chip Select. The Flash Chip Select pin provides an active low Flash chip select signal. This pin should be left floating if Flash is not used. Flash Output Enable. This pin provides an active low output enable control (read) to the Flash memory. This pin should be left floating if Flash is not used. Flash Write Enable. This pin provides an active low write enable control to the Flash memory. This pin should be left floating if Flash is not used.
FLA[1]/ AUXPWR
TS
FLA[0]/ PCIMODE#
TS
EECS
OUT
FLCS#
OUT
FLOE#
OUT
FLWE#
OUT
4.4
Table 6.
Test Port Signals
Test Port Signals
Symbol TEST TCK TI TEXEC TO Type IN IN IN IN OUT Name and Function Test Port. If this input pin is high, the 82551ER will enable the test port. During nominal operation this pin should be connected to a pulldown resistor. Test Port Clock. This pin is used for the Test Port Clock signal. Test Port Data Input. This pin is used for the Test Port Data Input signal. Test Port Execute Enable. This pin is used for the Test Port Execute Enable signal. Test Port Data Output. This pin is used for the Test Port Data Output signal.
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82551ER -- Networking Silicon
4.5
Table 7.
PHY Signals
PHY Signals
Symbol X1 Type AI Name and Function Crystal Input One. X1 and X2 can be driven by an external 3.3 V 25 MHz crystal. Otherwise, X1 may be driven by an external metal-oxide semiconductor (MOS) level 25 MHz oscillator when X2 is left floating. Crystal Input Two. X1 and X2 can be driven by an external 3.3 V 25 MHz crystal. Otherwise, X1 may be driven by an external MOS level 25 MHz oscillator when X2 is left floating. Analog Twisted Pair Ethernet Transmit Differential Pair. These pins transmit the serial bit stream for transmission on the Unshielded Twisted Pair (UTP) cable. The current-driven differential driver can be two-level (10BASE-T) or three-level (100BASE-TX) signals depending on the mode of operation. These signals interface directly with an isolation transformer. Analog Twisted Pair Ethernet Receive Differential Pair. These pins receive the serial bit stream from the isolation transformer. The bit stream can be two-level (10BASE-T) or three-level (100BASE-TX) signals depending on the mode of operation. Activity LED. The Activity LED pin indicates either transmit or receive activity. When activity is present, the activity LED is on (ACTLED# active low); when no activity is present, the activity LED is off. Link Integrity LED. The Link Integrity LED pin indicates link integrity. If the link is valid in either 10 or 100 Mbps, the LED is on (LILED# active low); if link is invalid, the LED is off. Speed LED. The Speed LED pin indicates the speed. The speed LED will be on at 100 Mbps (SPEEDLED# active low) and off at 10 Mbps. Reference Bias Resistor (100 Mbps). This pin should be connected to a 619 pull-down resistor.a Reference Bias Resistor (10 Mbps). This pin should be connected to a 549 pull-down resistor.b Voltage Reference. This pin is connected to a 1.25 V 1% external voltage reference generator. To use the internal voltage reference source, this pin should be left floating. Under normal circumstances, the internal voltage reference should be used and this pin would be left open.
X2
AO
TDP TDN
AO
RDP RDN
AI
ACTLED#
OUT
LILED#
OUT
SPEEDLED# RBIAS100 RBIAS10
OUT B B
VREF
B
a. 619 for RBIAS 100 is only a recommended value and should be fine tuned for specific designs. b. 549 for RBIAS 10 is only a recommended value and should be fine tuned for specific designs.
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Networking Silicon -- 82551ER
4.6
Table 8.
Power and Ground Signals
Power and Ground Signals
Symbol Type Name and Function Digital 3.3 V Power. The VCC pins should be connected to the main digital power supply. This is 3.3 VAUX in systems with an auxiliary power supply and PCI power in systems without an auxiliary power supply. The power source is configured through the FLA[1]/AUXPWR pin. Analog Power. These pins should be isolated from VCC with a resistor-capacitor (RC) filter. Digital Ground. These pins should be connected to the main digital ground plane. No Connect. These pins should not be connected to any circuit. Pullup or pull-down resistors should not be used.
VCC
DPS
VCCR VSSPL, VSSPP, VSSPT, VSS NC
APS
DPS
DPS
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82551ER -- Networking Silicon
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5.0
5.1
Media Access Control Functional Description
Device Initialization
The 82551ER has six sources for initialization. They are listed according to their precedence: 1. Internal Power-on Reset (POR) 2. ALTRST# pin 3. RST# pin 4. ISOLATE# pin 5. Software Reset (Software Command) 6. Selective Reset (Software Command)
5.1.1
Initialization Effects
The following table shows the effect of each of the different initialization sources on major portions of the 82551ER. The initialization sources are listed in order of precedence. For example, any resource that is initialized by the software reset is also initialized by the D3 to D0 transition and ALTRST# and PCI RST# but not necessarily by the selective reset.
Table 9.
Initialization Effects
Internal POR EEPROM read and initialization Loadable microcode decoded/reset MAC configuration reset and multicast hash Memory pointers and mircomachine state reset PCI Configuration register reset PHY configuration reset ALTRST# RST# ISOLATE# D3 to D0 Transition -Software Reset -Selective Reset --

--

--

--
--
--
--
--
--
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82551ER -- Networking Silicon
Table 9.
Initialization Effects
Internal POR Power management event reset Statistic counters reset Sampling of configuration input pins ALTRST# RST# Clear only if no auxiliary power present ISOLATE# Clear only if no auxiliary power present D3 to D0 Transition Software Reset Selective Reset
--
--
--

--
--
--
--
--
5.2
5.2.1
PCI Interface
Bus Operations
After configuration, the 82551ER is ready for its normal operation. As a Fast Ethernet Controller, the role of the 82551ER is to access transmitted data or deposit received data. In both cases the 82551ER, as a bus master device, will initiate memory cycles by way of the PCI bus. To perform these actions, the 82551ER is controlled and examined by the CPU through its control and status structures and registers. Some of these structures reside in the 82551ER and some reside in system memory. For access to the 82551ER's Control/Status Registers (CSR), the 82551ER acts as a slave device. The 82551ER serves as a slave also while the CPU accesses its 128 Kbyte Flash buffer or its EEPROM. Section 5.2.1.1 describes the 82551ER slave operation. It is followed by a description of the 82551ER operation as a bus master (initiator) in Section 5.2.1.2.
5.2.1.1
Bus Slave Operation
The 82551ER serves as a target device in the following cases:
* * * * * *
CPU accesses to the 82551ER System Control Block (SCB) Control/Status Registers (CSR) CPU accesses to the EEPROM through its CSR CPU accesses to the 82551ER PORT address through the CSR CPU accesses to the MDI control register in the CSR CPU accesses to the Flash control register in the CSR CPU accesses to the 128 Kbyte Flash
The CSR and the 1 Mbyte Flash buffer are considered by the 82551ER as totally separated memory spaces. The 82551ER provides separate Base Address Registers (BARs) in the configuration space to distinguish between them. The size of the CSR memory space is 4 Kbyte in the memory space and 64 bytes in the I/O space. The 82551ER treats accesses to these memory spaces differently.
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Networking Silicon -- 82551ER
5.2.1.1.1
Control/Status Register (CSR) Accesses
The 82551ER supports zero wait state single cycle memory or I/O mapped accesses to its CSR space. Separate BARs request 4 Kbytes of memory space and 64 bytes of I/O space to accomplish these accesses. The 82551ER provides 4 valid Kbytes of CSR space, which include the following elements:
* * * * * *
System Control Block (SCB) registers PORT register Flash control register EEPROM control register MDI control register Flow control registers
The following figures show CSR zero wait state I/O read and write cycles. In the case of accessing the Control/Status Registers, the CPU is the initiator and the 82551ER is the target of the transaction.
Figure 1. CSR I/O Read Cycle
CLK
1 2 3 4 5 6 7 8 9
SYSTEM
FRAME# AD C/BE# IRDY# TRDY#
ADDR DATA
I/O RD
BE#
82551ER
DEVSEL# STOP#
Read Accesses: The CPU, as the initiator, drives address lines AD[31:0], the command and byte enable lines C/BE[3:0]# and the control lines IRDY# and FRAME#. As a slave, the 82551ER controls the TRDY# signal and provides valid data on each data access. The 82551ER allows the CPU to issue only one read cycle when it accesses the Control/Status Registers, generating a disconnect by asserting the STOP# signal. The CPU can insert wait states by de-asserting IRDY# when it is not ready.
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82551ER -- Networking Silicon
Figure 2. CSR I/O Write Cycle
CLK
1 2 3 4 5 6 7 8 9
SYSTEM
FRAME# AD C/BE# IRDY# TRDY#
ADDR DATA
I/O WR
BE#
82551ER
DEVSEL# STOP#
Write Accesses: The CPU, as the initiator, drives the address lines AD[31:0], the command and byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. It also provides the 82551ER with valid data on each data access immediately after asserting IRDY#. The 82551ER controls the TRDY# signal and asserts it from the data access. The 82551ER allows the CPU to issue only one I/O write cycle to the Control/Status Registers, generating a disconnect by asserting the STOP# signal. This is true for both memory mapped and I/O mapped accesses.
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5.2.1.1.2
Flash Buffer Accesses
The CPU accesses to the Flash buffer are very slow and the 82551ER issues a target-disconnect at the first data access. The 82551ER asserts the STOP# signal to indicate a target-disconnect. The figures below illustrate memory CPU read and write accesses to the 128 Kbyte Flash buffer. The longest burst cycle to the Flash buffer contains one data access only. Figure 3. Flash Buffer Read Cycle
CLK FRAME# AD C/BE# IRDY# TRDY#
ADDR DATA
SYSTEM
MEM RD
BE#
82551ER
DEVSEL# STOP#
Read Accesses: The CPU, as the initiator, drives the address lines AD[31:0], the command and byte enable lines C/BE[3:0]# and the control lines IRDY# and FRAME#. The 82551ER controls the TRDY# signal and de-asserts it for a certain number of clocks until valid data can be read from the Flash buffer. When TRDY# is asserted, the 82551ER drives valid data on the AD[31:0] lines. The CPU can also insert wait states by de-asserting IRDY# until it is ready. Flash buffer read accesses can be byte or word length.
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82551ER -- Networking Silicon
Figure 4. Flash Buffer Write Cycle
CLK FRAME# AD C/BE# IRDY# TRDY#
ADDR DATA
SYSTEM
MEM WR
BE#
82551ER
DEVSEL# STOP#
Write Accesses: The CPU, as the initiator, drives the address lines AD[31:0], the command and byte enable lines C/BE[3:0]# and the control lines IRDY# and FRAME#. It also provides the 82551ER with valid data immediately after asserting IRDY#. The 82551ER controls the TRDY# signal and deasserts it for a certain number of clocks until valid data is written to the Flash buffer. By asserting TRDY#, the 82551ER signals the CPU that the current data access has completed. Flash buffer write accesses can be byte length only.
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5.2.1.1.3
Retry Premature Accesses
The 82551ER responds with a Retry to any configuration cycle accessing the 82551ER before the completion of the automatic read of the EEPROM. The 82551ER may continue to Retry any configuration accesses until the EEPROM read is complete. The 82551ER does not enforce the rule that the retry master must attempt to access the same address again to complete any delayed transaction. Any master access to the 82551ER after the completion of the EEPROM read will be honored. Figure 5 below depicts how a Retry looks when it occurs. Figure 5. PCI Retry Cycle SYSTEM
CLK FRAME# IRDY# TRDY#
82551ER
DEVSEL# STOP#
Note:
The 82551ER is considered the target in the above diagram; thus, TRDY# is not asserted.
5.2.1.1.4
Error Handling
Data Parity Errors: The 82551ER checks for data parity errors while it is the target of the transaction. If an error was detected, the 82551ER always sets the Detected Parity Error bit in the PCI Configuration Status register, bit 15. The 82551ER also asserts PERR#, if the Parity Error Response bit is set (PCI Configuration Command register, bit 6). The 82551ER does not attempt to terminate a cycle in which a parity error was detected. This gives the initiator the option of recovery. Target-Disconnect: The 82551ER prematurely terminates a cycle in the following cases:
* After accesses to the Flash buffer * After accesses to its CSR * After accesses to the configuration space
System Error: The 82551ER reports parity error during the address phase using the SERR# pin. If the SERR# Enable bit in the PCI Configuration Command register or the Parity Error Response bit is not set, the 82551ER only sets the Detected Parity Error bit (PCI Configuration Status register, bit 15). If SERR# Enable and Parity Error Response bits are both set, the 82551ER sets the Signaled System Error bit (PCI Configuration Status register, bit 14) as well as the Detected Parity Error bit and asserts SERR# for one clock.
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82551ER -- Networking Silicon
Note:
The 82551ER detects a system error for any parity error during an address phase, whether or not it is involved in the current transaction.
5.2.1.2
Bus Master Operation
As a PCI Bus Master, the 82551ER initiates memory cycles to fetch data for transmission or deposit received data and to access the memory resident control structures. The 82551ER performs zero wait state burst read and write cycles to the host main memory. Figure 6 and Figure 7 depict memory read and write burst cycles. For bus master cycles, the 82551ER is the initiator and the host main memory (or the PCI host bridge, depending on the configuration of the system) is the target.
Figure 6. Memory Read Burst Cycle
CLK
1 2 3 4 5 6 7 8 9 10
FRAME#
82551ER
AD C/BE# IRDY#
ADDR
DATA
DATA
DATA
DATA
DATA
MR
BE#
BE#
SYSTEM
TRDY# DEVSEL#
Figure 7. Memory Write Burst Cycle
CLK
1 2 3 4 5 6 7 8 9 10
FRAME#
82551ER
AD C/BE# IRDY#
ADDR
DATA
DATA
DATA
DATA
DATA
MW
BE#
BE#
SYSTEM 22
TRDY# DEVSEL#
The CPU provides the 82551ER with action commands and pointers to the data buffers that reside in host main memory. The 82551ER independently manages these structures and initiates burst memory cycles to transfer data to and from them. The 82551ER uses the Memory Read Multiple (MR Multiple) command for burst accesses to data buffers and the Memory Read Line (MR Line)
Datasheet
Networking Silicon -- 82551ER
command for burst accesses to control structures. For all write accesses to the control structure, the 82551ER uses the Memory Write (MW) command. For write accesses to data structure, the 82551ER may use either the Memory Write or Memory Write and Invalidate (MWI) commands. Read Accesses: The 82551ER performs block transfers from host system memory to perform frame transmission on the serial link. In this case, the 82551ER initiates zero wait state memory read burst cycles for these accesses. The length of a burst is bounded by the system and the 82551ER's internal FIFO. The length of a read burst may also be bounded by the value of the Transmit DMA Maximum Byte Count in the Configure command. The Transmit DMA Maximum Byte Count value indicates the maximum number of transmit DMA PCI cycles that will be completed after an 82551ER internal arbitration. The 82551ER, as the initiator, drives the address lines AD[31:0], the command and byte enable lines C/BE[3:0]# and the control lines IRDY# and FRAME#. The 82551ER asserts IRDY# to support zero wait state burst cycles. The target signals the 82551ER that valid data is ready to be read by asserting the TRDY# signal. Write Accesses: The 82551ER performs block transfers to host system memory during frame reception. In this case, the 82551ER initiates memory write burst cycles to deposit the data, usually without wait states. The length of a burst is bounded by the system and the 82551ER's internal FIFO threshold. The length of a write burst may also be bounded by the value of the Receive DMA Maximum Byte Count in the Configure command. The Receive DMA Maximum Byte Count value indicates the maximum number of receive DMA PCI transfers that will be completed before the 82551ER internal arbitration. The 82551ER, as the initiator, drives the address lines AD[31:0], the command and byte enable lines C/BE[3:0]# and the control lines IRDY# and FRAME#. The 82551ER asserts IRDY# to support zero wait state burst cycles. The 82551ER also drives valid data on AD[31:0] lines during each data phase (from the first clock and on). The target controls the length and signals completion of a data phase by de-assertion and assertion of TRDY#.
5.2.1.2.1
Memory Write and Invalidate
The 82551ER has four Direct Memory Access (DMA) channels. Of these four channels, the Receive DMA is used to deposit the large number of data bytes received from the link into system memory. The Receive DMA uses both the Memory Write (MW) and the Memory Write and Invalidate (MWI) commands. To use MWI, the 82551ER must guarantee the following: 1. Minimum transfer of one cache line 2. Active byte enable bits (or BE[3:0]# are all low) during MWI access 3. The 82551ER may cross the cache line boundary only if it intends to transfer the next cache line too. To ensure the above conditions, the 82551ER may use the MWI command only if the following conditions are true: 1. The Cache Line Size (CLS) written in the CLS register during PCI configuration is 8 or 16 Dwords. 2. The accessed address is cache line aligned. 3. The 82551ER has at least 8 or 16 Dwords of data in its receive FIFO. 4. There are at least 8 or 16 Dwords of data space left in the system memory buffer. 5. The MWI Enable bit in the PCI Configuration Command register, bit 4, must be set to 1b.
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82551ER -- Networking Silicon
6. The MWI Enable bit in the 82551ER Configure command must be set to 1b. If any one of the above conditions is not true, the 82551ER uses the MW command. If an MWI cycle has started and one of the conditions is no longer valid (for example, the data space in the memory buffer is now less than CLS), then the 82551ER terminates the MWI cycle at the end of the cache line. The next cycle is either an MW or MWI cycle depending on the conditions listed above. If the 82551ER started a MW cycle and reached a cache line boundary, it either continues or terminates the cycle depending on the Terminate Write on Cache Line configuration bit of the 82551ER Configure command (byte 3, bit 3). If this bit is set, the 82551ER terminates the MW cycle and attempts to start a new cycle. The new cycle is an MWI cycle if this bit is set and all of the above conditions are met. If the bit is not set, the 82551ER continues the MW cycle across the cache line boundary if required.
5.2.1.2.2
Read Align
The Read Align feature enhances the 82551ER's performance in cache line oriented systems. In these particular systems, starting a PCI transaction on a non-cache line aligned address may cause low performance. To resolve this performance anomaly, the 82551ER attempts to terminate transmit DMA cycles on a cache line boundary and start the next transaction on a cache line aligned address. This feature is enabled when the Read Align Enable bit is set in the 82551ER Configure command (byte 3, bit 2). If this bit is set, the 82551ER operates as follows:
* When the 82551ER is almost out of resources on the transmit DMA (that is, the transmit FIFO
is almost full), it attempts to terminate the read transaction on the nearest cache line boundary.
* When the arbitration counter's feature is enabled (in other words, the Transmit DMA
Maximum Byte Count value is set in the Configure command), the 82551ER switches to other pending DMAs on cache line boundary only. This feature is not recommended for use in non-cache line oriented systems since it may cause shorter bursts and lower performance. If this feature is used, it is recommended that the CLS register in PCI Configuration space is set to 8 or 16.
5.2.1.2.3
Error Handling
Data Parity Errors: As an initiator, the 82551ER checks and detects data parity errors that occur during a transaction. If the Parity Error Response bit is set (PCI Configuration Command register, bit 6), the 82551ER also asserts PERR# and sets the Data Parity Detected bit (PCI Configuration Status register, bit 8). In addition, if the error was detected by the 82551ER during read cycles, it sets the Detected Parity Error bit (PCI Configuration Status register, bit 15).
5.2.2
Clockrun Signal
This signal is active in PCI bus operating modes. The Clockrun signal is an open drain I/O signal. It is used as a bidirectional channel between the host and the devices.
* The host de-asserts the CLKRUN# signal to indicate that the clock is about to be stopped or
slowed down to a non-operational frequency.
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* The host asserts the CLKRUN# signal when the clock is either running at a normal operating
frequency or about to be started.
* The 82551ER asserts the CLKRUN# signal to indicate that the PCI clock must prevent the
host from stopping or to request that the host restore the clock if it was previously stopped. Proper operation requires that the system latency from the nominal PCI CLK to CLKRUN# assertion should be less than 0.5 s. If the system latency is longer than 0.5 s, there is an increase in receive overruns. In these types of systems, the Clockrun functionality should be disabled. In this case, the 82551ER will claim the PCI clock even during idle time. If the CLKRUN# signal is not used, it must be connected to a pull-down resistor.
5.2.3
Power Management Event
The 82551ER supports power management indications in the PCI mode. The PME# output pin provides an indication of a power management event in PCI systems.
5.3
PCI Power Management
The 82551ER supports interesting packet wake-up and the capability to wake the system on a link status change from a low power state. The 82551ER enables the host system to be in a sleep state and remain virtually connected to the network. After a power management event or link status change is detected, the 82551ER will wake the host system. The sections below describe these events, the 82551ER power states, and estimated power consumption at each power state.
5.3.1
Power States
The 82551ER has one set of PCI power management registers and implements all four power states as defined in the Power Management Network Device Class Reference Specification, Revision 1.0. The four device power states, D0 through D3, vary from maximum power consumption at D0 to the minimum power consumption at D3. PCI transactions are only allowed in the D0 state, except for host accesses to the 82551ER's PCI configuration registers. The D1 and D2 power management states enable intermediate power savings while providing the system wake-up capabilities. In the D3 cold state, the 82551ER can provide wake-up capabilities only if auxiliary power is supplied. Wake-up indications from the 82551ER are provided by the Power Management Event (PME#) signal in PCI implementations
5.3.1.1
D0 Power State
As defined in the Network Device Class Reference Specification, the device is fully functional in the D0 power state. In this state, the 82551ER receives full power and should be providing full functionality. In the 82551ER the D0 state is partitioned into two substates, D0 Uninitialized (D0u) and D0 Active (D0a). D0u is the 82551ER's initial power state following a Power-on Reset (POR) event and before the Base Address Registers (BARs) are accessed. Initialization of the CSR, Memory, or I/O Base Address Registers in the PCI Configuration space switches the 82551ER from the D0u state to the D0a state.
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82551ER -- Networking Silicon
In the D0a state, the 82551ER provides its full functionality and consumes nominal power. In addition, the 82551ER supports wake on link status change (Section 5.3.2, "Wake-up Events"). While it is active, the 82551ER requires a nominal PCI clock signal (in other words, a clock frequency greater than 16 MHz) for proper operation. During idle time, the 82551ER supports a PCI clock signal suspension using the Clockrun signal mechanism. The 82551ER supports a dynamic standby mode. In this mode, the 82551ER is able to save almost as much power as it does in the static power-down states. The transition to or from standby is done dynamically by the 82551ER and is transparent to the software.
5.3.1.2
D1 Power State
For a device to meet the D1 power state requirements, as specified in the Advanced Configuration and Power Interface (ACPI) Specification, Revision 1.0, it must not allow bus transmission or interrupts; however, bus reception is allowed. Therefore, device context may be lost and the 82551ER does not initiate any PCI activity. In this state, the 82551ER responds only to PCI accesses to its configuration space and system wake-up events. The 82551ER retains link integrity and monitors the link for any wake-up events such as wake-up packets or link status change. Following a wake-up event, the 82551ER asserts the PME# signal to alert the PCI system.
5.3.1.3
D2 Power State
The ACPI D2 power state is similar in functionality to the D1 power state. If the bus is in the B2 bus power state, the 82551ER will consume less current than it does in the D1 state. In addition to D1 functionality, the 82551ER can provide a lower power mode with wake-on-link status change capability. The 82551ER may enter this mode if the link is down while the 82551ER is in the D2 state. In this state, the 82551ER monitors the link for a transition from an invalid link to a valid link. The 82551ER will not attempt to keep the link alive by transmitting idle symbols or link integrity pulses.1 The sub-10 mA state due to an invalid link can be enabled or disabled by a configuration bit in the Power Management Driver Register (PMDR).
5.3.1.4
D3 Power State
In the D3 power state, the 82551ER has the same capabilities and consumes the same amount of power as it does in the D2 state. However, it enables the PCI system to be in the Bus Power 3 (B3) state. If the PCI system is in the B3 state (in other words, no PCI power is present), the 82551ER provides wake-up capabilities if it is connected to an auxiliary power source in the system. If PME is disabled, the 82551ER does not provide wake-up capability or maintain link integrity. In this mode, the 82551ER consumes minimal power. The 82551ER enables a system to be in a sub-5 watt state (low power state) and still be virtually connected. More specifically, the 82551ER supports full wake-up capabilities while it is in the D3 cold state. The 82551ER can be connected to an auxiliary power source (VAUX), which enables it to provide wake-up functionality while the PCI power is off. The typical current consumption of the 82551ER is 125 mA at 3.3 V and a dual power plane is not required. If connected to an auxiliary power source, the 82551ER receives all of its power from the auxiliary source in all power states. When connected to an auxiliary power supply, the 82551ER must have a status indicator of whether the power supply is valid (in other words, auxiliary power is stable). The indication is received at the AUXPWR pin, as described next.
1. For a topology of two 82551ER devices connected by a crossed twisted-pair Ethernet cable, the deep power-down mode should be disabled. If it is enabled, the two devices may not detect each other if the operating system places them into a low power state before both nodes become active.
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5.3.1.4.1
Auxiliary Power Signal
The 82551ER senses whether it is connected to the PCI power supply or to an auxiliary power supply (VAUX) through the FLA1/AUXPWR pin. The auxiliary power detection pin (multiplexed with FLA1) is sampled when the 82551ER power-on reset is active. An external pull-up resistor should be connected to the 82551ER if it is fed by VAUX; otherwise, the FLA1/AUXPWR pin should be left floating. The presence of AUXPWR affects the value reported in the Power Management Capability Register (PCI Configuration Space, offset DEh). The Power Management Capability Register is described in more detail in Section 9.1.20, "Power Management Capabilities Register".
5.3.1.4.2
Alternate Reset Signal
The 82551ER's ALTRST# input pin functions as a power-on reset input. Following ALTRST# being driven low, the 82551ER is initialized to a known state. While this function is required, this pin is not needed for it. Since this functionality is provided by the 82551ER's internal power-on reset signal, this pin should be pulled high to the main digital power supply. Note: A separate internal power-on reset signal is generated when power is applied to the device. This signal is active while it provides the 82551ER power-on reset function and is also used for sampling configuration inputs.
5.3.1.4.3
Isolate Signal
When the 82551ER is connected to VAUX, it can be powered on while the PCI bus is powered off. In this case, the 82551ER isolates itself from the PCI bus. The 82551ER has a dedicated ISOLATE# pin that must be connected to the PCI Reset signal. Whenever the PCI Bus is in the B3 state, the PCI Reset signal becomes active and the 82551ER isolates itself from the PCI bus. During this state, the 82551ER ignores all PCI signals including the RST# and CLK input signals. It also tristates all PCI outputs, except the PME# signal. In the transition to an active PCI power state (in other words, from B3 bus power state to B0 bus power state), the PCI Reset signal shifts high. This generates an internal hardware reset, which initializes the device (described in Section 5.1.1, "Initialization Effects"). Some designs in existence may implement the previous recommendations for the RST#, ISOLATE# and ALTRST# input pins. In these cases, the PCI Reset signal is connected to the RST# pin, the PCI power source's stable power (power good) to the ISOLATE# pin, and the auxiliary power source's stable power (auxiliary power good) to the ALTRST# pin. It is not necessary for existing working designs to make changes for these signals; however, it is recommended that the changes contained in this document should be included when possible. New designs should implement the recommendations contained in this document.
5.3.1.4.4
PCI Reset Signal
The PCI RST# signal can be activated in one of the following cases:
* * * *
Power-up Warm boot Wake-up (B3 to B0 transition) Set to power-down (B0 to B3 transition)
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If PME is enabled (in the PCI power management registers), the RST# signal does not affect any PME related circuits (in other words, PCI power management registers, and the wake-up packet would not be affected). Note: The PCI Specification, Revision 2.2, states that the PCI RST# signal should be active low in the B3 state. (In PCI Specification, Revision 2.1, the PCI RST# signal is undefined during the B3 state.) The transition from the B3 bus power state to the B0 bus power state occurs on the trailing edge of the PCI RST# signal. The initialization signal is generated internally in the following cases:
* Active RST# signal while the 82551ER is the D0, D1, or D2 power state * RST# trailing edge while the 82551ER is in the D3 power state * ISOLATE# trailing edge
The internal initialization signal resets the PCI Configuration Space, MAC configuration, and memory structure. The behavior of the RST# and ISOLATE# pins and the internal 82551ER initialization signal are shown in the following figure. Figure 8. Initialization upon RST# and ISOLATE#
D0 - D2 power state
RST# Internal hardware reset
D3 power state
RST# Internal hardware reset
Internal reset due to ISOLATE#
640 ns
ISOLATE# Internal hardware reset
640 ns
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The following tables summarizes the functionality at the different power states for the 82551ER. . Table 10. Functionality at the Different Power States
Power State D0u Link Don't care Valid D0a Invalid Valid D1 Invalid Valid D2 Invalid Valid D3 (with power) Invalid Dx (x>0 without PME#) Don't care Detection for valid link and no link integrity No wake-up functionality Detection for valid link and no link integrity Same functionality as D1 (link valid) * * Wake on link valid PCI configuration access Full functionality at full power and wake on a valid link * * Wake-up on "interesting" packets and link invalid PCI configuration access * * Power-up state PCI slave access Functionality
Full functionality at full power and wake on an invalid link
Same functionality as D1 (link valid)
5.3.2
Wake-up Events
There are two types of wake-up events: "Interesting" Packets and Link Status Change. These two events are detailed below. Note: The wake-up event is supported only if the PME Enable bit in the Power Management Control/ Status (PMCSR) register is set. The PMCSR is described in Section 9.1.21, "Power Management Control/Status Register (PMCSR)".
5.3.2.1
"Interesting" Packet Event
In the power-down state, the 82551ER is capable of recognizing "interesting" packets. The 82551ER supports pre-defined and programmable packets that can be defined as any of the following:
* * * * *
Address Resolution Protocol (ARP) Packets (with Multiple IP addresses) Direct Packets (with or without type qualification) Neighbor Discovery Multicast Address Packet ("ARP" in IPv6 environment) NetBIOS over TCP/IP (NBT) Query Packet (under IPv4) Internetwork Package Exchange* (IPX*) Diagnostic Packet
This allows the 82551ER to handle various packet types. In general, the 82551ER supports programmable filtering of any packet in the first 128 bytes.
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5.3.2.2
Link Status Change Event
The 82551ER link status indication circuit is capable of issuing a PME on a link status change from a valid link to an invalid link condition or vice versa. The 82551ER reports a PME link status event in all power states. The PME# signal is gated by the PME Enable bit in the PMCSR and the CSMA Configure command.
5.4
Parallel Flash
The 82551ER's parallel interface is used for Flash interface. The 82551ER supports a glueless interface to an 8-bit wide, 128 Kbyte, parallel memory device. The Flash (or boot PROM) is read from or written to whenever the host CPU performs a read or a write operation to a memory location that is within the Flash mapping window. All accesses to the Flash, except read accesses, require the appropriate command sequence for the device used. (Refer to the specific Flash data sheet for more details on reading from or writing to the Flash device.) The accesses to the Flash are based on a direct decode of CPU accesses to a memory window defined in either the 82551ER Flash Base Address Register (PCI Configuration space at offset 18h) or the Expansion ROM Base Address Register (PCI Configuration space at offset 30h). The 82551ER asserts control to the Flash when it decodes a valid access. The 82551ER supports an external Flash memory (or boot PROM) of up to 128 Kbyte. The Expansion ROM address can be separately disabled by setting the corresponding bit in the EEPROM, word Ah. Note: Flash accesses must always be assembled or disassembled by the 82551ER whenever the access is greater than a byte-wide access. Due to slow access times to a typical Flash and to avoid violating PCI bus holding specifications (no more than 16 wait states inserted for any cycles that are not system initiation cycles), the maximum data size is either one word or one byte for a read operation and one byte only for a write operation.
5.5
Serial EEPROM Interface
The serial EEPROM stores configuration data for the 82551ER and is a serial in/serial out device. The 82551ER supports either a 64-register or 256-register size EEPROM and automatically detects the EEPROM's size. A 256-word EEPROM device is required for a TCO enabled system to hold the heartbeat packet. The EEPROM should operate at a frequency of at least 1 MHz.
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All accesses, either read or write, are preceded by a command instruction to the device. The address field is six bits for a 64-register EEPROM or eight bits for a 256-register EEPROM. The end of the address field is indicated by a dummy zero bit from the EEPROM, which indicates the entire address field has been transferred to the device. An EEPROM read instruction waveform is shown in the figure below. Figure 9. 64-Word EEPROM Read Instruction Waveform
EESK
EECS
A5 EEDI READ OP code
A4
A3
A2
A10 A
A0
D15 EEDO
D0
The 82551ER can also use the EEPROM for heartbeat packet transmission (systems without a TCO controller are also supported). In these designs, the EEPROM is accessed through time windows autonomously by the 82551ER hardware. During these time windows, the 82551ER will respond with a PCI Retry to both EEPROM and Flash accesses. The 82551ER performs an automatic read of five words (0h, 1h, 2h, Ah, and Dh) of the EEPROM after the de-assertion of Reset. The 82551ER EEPROM format is shown below in Table 11. Table 11. EEPROM Address Map
Word 00h 01h 02h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh FBh - FEh FFh High Byte (Bits 15 - 8) Ethernet Individual Address Byte 2 Ethernet Individual Address Byte 4 Ethernet Individual Address Byte 6 EEPROM_ID (high byte) Subsystem_ID (high byte) Subsystem_Vendor (high byte) Reserved Reserved Reserved Reserved 256-word EEPROM Checksum (high byte) 256-word EEPROM Checksum (low byte) Low Byte (Bits 7 - 0) Ethernet Individual Address Byte 1 Ethernet Individual Address Byte 3 Ethernet Individual Address Byte 5 EEPROM_ID (low byte) Subsystem_ID (low byte) Subsystem_Vendor (low byte) Reserved Reserved Reserved
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Note:
Word Ah contains several configuration bits. Bits from word Ah, FBh through FEh, and certain bits from word Dh are described as follows:
Table 12. EEPROM Words Field Descriptions
Bits Word Ah, 15:14 Name Signature Description The Signature field is a signature of 01b, indicating to the 82551ER that there is a valid EEPROM present. If the Signature field is not 01b, the other bits are ignored and the default values are used. The default configuration values are: * Revision ID (01b) * Standby mode disabled * Deep power-down enabled * Boot ROM enabled and boot expansion ROM base address register disabled * Subsystem ID and System Vendor ID set to 00b Word Ah, 13 ID The ID bit indicates how the Subsystem ID and Subsystem Vendor ID fields are used as described in Section 9.1.12, "PCI Subsystem Vendor ID and Subsystem ID Registers". Default value is 0b. If the controller detects the presence of a valid EEPROM (Signature bits equal 01b), the following operations are performed depending on the value of the ID bit: `0' The PCI Device ID is loaded with the contents of word 23h, and the PCI Vendor ID is loaded with the contents of word 0Ch. `1' The PCI Device ID is loaded with the contents of word 23h, and the PCI Vendor ID is loaded with the value 8086h. Word Ah, 12 Word Ah, 11 Word Ah, 10:8 Reserved Boot Disable This bit is reserved and should be set to 0b. The Boot Disable bit disables the Expansion ROM Base Address Register (PCI Configuration space, offset 30h) when it is set to 1b. Default value is 0b. These three bits are used as the three least significant bits of the device revision, if bits 15, 14, and 13 equal 011b and the ID was set as described in Section 9.1.12, "PCI Subsystem Vendor ID and Subsystem ID Registers". The default value depends on the silicon revision. Note: The Alternate Revision ID field in the EEPROM is active only if the ID bit (bit 13) is set to 1b. The default value for this field is 000b. Word Ah, 7 Word Ah, 6 Reserved Deep Power Down This field is reserved and should be set to 0b. Disable Deep Power Down in the D2 or D3 states when PME is disabled: `0' Deep Power Down is enabled in D3 state if PME is disabled. `1' Deep Power Down disabled in D3 state when PME is disabled. Word Ah, 5:2 Word Ah, 1 Reserved Standby Enable These bits are reserved and should be set to 0000b. The Standby Enable bit enables the 82551ER to enter standby mode. When this bit equals 1b, the 82551ER is able to recognize an idle state and can enter standby mode (some internal clocks are stopped for power saving purposes). If this bit equals 0b, the idle recognition circuit is disabled and the 82551ER always remains in an active state. Note: The 82551ER does not require a PCI clock signal in standby mode and always request PCI CLK using the Clockrun mechanism. Word Ah, 0 Reserved This bit is reserved and should be set to 0b.
Alternate Revision ID
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Note:
The IA read from the EEPROM is used by the 82551ER until an IA Setup command is issued by software. The IA defined by the IA Setup command overrides the IA read from the EEPROM.
5.6
10/100 Mbps CSMA/CD Unit
The 82551ER CSMA/CD unit implements both the IEEE 802.3 Ethernet 10 Mbps and IEEE 802.3u Fast Ethernet 100 Mbps standards. It performs all the CSMA/CD protocol functions such as transmission, reception, collision handling, etc. The 82551ER CSMA/CD unit communicates with the internal PHY unit through a standard Media Independent Interface (MII), as specified by IEEE 802.3, Chapter 22. This is a 10/100 Mbps mode in which the data stream is nibble-wide and the serial clocks run at either 25 or 2.5 MHz.
5.6.1
Full Duplex
When operating in full duplex mode the 82551ER can transmit and receive frames simultaneously. Transmission starts regardless of the state of the internal receive path. Reception starts when the internal PHY detects a valid frame on the receive differential pair of the PHY. The 82551ER operates in either half duplex mode or full duplex mode. For proper operation, both the 82551ER CSMA/CD module and the PHY unit must be set to the same duplex mode. The CSMA duplex mode is set by the 82551ER Configure command or forced by the settings in the PHY unit's registers. The PHY duplex mode is set either by Auto-Negotiation or, if Auto-Negotiation is disabled, by setting the full duplex bit in the Management Data Interface (MDI) Register 0, bit 8. By default, the internal PHY unit advertises full duplex ability in the Auto-Negotiation process regardless of the duplex setting of the CSMA unit. The CSMA configuration should match the result of the AutoNegotiation. The selection of duplex operation (full or half) and flow control is done in two levels: MAC and PHY. The MAC duplex selection is done only through the CSMA configuration mechanism (in other words, the Configure command in software).
5.6.2
Flow Control
The 82551ER supports IEEE 802.3x frame-based flow control frames in both full duplex and half duplex switched environments. The 82551ER flow control feature is not intended to be used in shared media environments. The PHY unit's duplex and flow control enable can be selected using the NWay* Auto-Negotiation algorithm or through the Management Data Interface.
5.6.3
Address Filtering Modifications
The 82551ER can be configured to ignore one bit when checking for its Individual Address (IA) on incoming receive frames. The address bit, known as the Upper/Lower (U/L) bit, is the second least significant bit of the first byte of the IA. This bit may be used, in some cases, as a priority indication bit. When configured to do so, the 82551ER passes any frame that matches all other 47 address bits of its IA, regardless of the U/L bit value.
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This configuration only affects the 82551ER specific IA and not multicast, multi-IA or broadcast address filtering. The 82551ER does not attribute any priority to frames with this bit set, it simply passes them to memory regardless of this bit.
5.6.4
Long Frame Reception
The 82551ER controller supports the reception of frames longer than 1518 bytes, including the CRC, if software sets the Long Receive OK bit in the Configuration Command. Otherwise, long frames are discarded.
5.7
Media Independent Interface (MII) Management Interface
The MII management interface allows the CPU to control the PHY unit through a control register in the 82551ER. This allows the software driver to place the PHY in specific modes such as full duplex, loopback, power down, etc., without the need for specific hardware pins to select the desired mode. This structure allows the 82551ER to query the PHY unit for status of the link. This register is the MDI Control Register and resides at offset 10h in the 82551ER CSR. (The MDI registers are described in detail in Section 11.0, "PHY Unit Registers".) The CPU writes commands to this register and the 82551ER reads or writes the control/status parameters to the PHY unit through the MDI register. Although the 82551ER follows the MII format, the MI bus is not accessible on external pins.
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6.0
6.1
6.1.1
Physical Layer Functional Description
100BASE-TX PHY Unit
100BASE-TX Transmit Clock Generation
A 25 MHz crystal or a 25 MHz oscillator is used to drive the PHY unit's X1 and X2 pins. The PHY unit derives its internal transmit digital clocks from this crystal or oscillator input. The internal Transmit Clock signal is a derivative of the 25 MHz internal clock. The accuracy of the external crystal or oscillator must be 0.005% (50 PPM).
6.1.2
100BASE-TX Transmit Blocks
The transmit subsection of the PHY unit accepts nibble-wide data from the CSMA/CD unit. The transmit subsection passes data unconditionally to a 4B/5B encoder. The 4B/5B encoder accepts nibble-wide data (4 bits) from the CSMA unit and compiles it into 5bit-wide parallel symbols according to the IEEE 802.3u 100BASE_TX standard. Next, the symbols are scrambled to reduce electromagnetic emissions during long sequences of high-frequency data codes. The MLT-3 (multi-level signal) encoder receives the scrambled Non-Return to Zero (NRZ) data stream from the scrambler and encodes the stream into MLT-3 for presentation to the driver. MLT-3 is similar to NRZ1 coding, but three levels are output instead of two. The three output levels are positive, negative and zero. The transmit differential pair line drivers are implemented with digital slope controlled current buffers that meet the TP-PMD specifications. Current is sinked from an isolation transformer by the TDP and TDN pins. The 125 Mbps bit stream is typically driven onto Unshielded Twisted Pair (UTP) cable.
6.1.3
100BASE-TX Receive Blocks
The receive subsection of the PHY unit accepts 100BASE-TX MLT-3 data on the receive differential pair. Due to the advanced digital signal processing design techniques employed, the PHY unit will accurately receive valid data from Category 5 (CAT5) UTP cables of lengths well in excess of 100 meters. The distorted distorted MLT-3 signal at the end of the wire is restored by the equalizer. The equalizer performs adaptation based on the shape of the received signal. The clock recovery circuit uses digital signal processing to compensate for various signal jitter causes. The circuit recovers the 125 MHz clock and data and presents the data to the MLT-3 decoder. The PHY unit first decodes the MLT-3 data; afterwards, the descrambler reproduces the 5B symbols originated in the transmitter. The data is decoded at the 4B/5B decoder. After the 4B symbols are obtained, the PHY unit outputs the receive data to the CSMA unit. In 100BASE-TX mode, the PHY unit can detect errors in receive data in a number of ways, including link integrity failures, undetected start of stream delimiters, invalid symbols, or idles in the middle of a frame.
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6.1.4
100BASE-TX Link Integrity Auto-Negotiation
The 82551ER Auto-Negotiation function automatically configures the device to the technology, media, and speed to operate with its link partner. Auto-Negotiation is described in IEEE specification 802.3u, clause 28. The PHY unit supports 10BASE-T half duplex, 10BASE-T full duplex, 100BASE-TX half duplex, and 100BASE-TX full duplex. Speed and duplex auto-select are functions of Auto-Negotiation. However, these parameters may be manually configured through the MII management interface (MDI registers). Manual configurations override the auto-select.
6.2
6.2.1
10BASE-T PHY Functions
10BASE-T Transmit Clock Generation
The 20 MHz and 10 MHz clocks needed for 10BASE-T are synthesized from the external 25 MHz crystal or oscillator. The PHY unit provides the transmit clock and receive clock to the internal MAC at 2.5 MHz.
6.2.2
10BASE-T Transmit Blocks
After the 2.5 MHz clocked data is serialized in a 10 Mbps serial stream, the 20 MHz clock performs Manchester encoding. Since 10BASE-T and 100BASE-TX have different filtration needs, both filters are implemented inside the chip. The PHY unit supports both technologies through one pair of TD pins and by externally sharing the same magnetics. In 10 Mbps mode, the line drivers use a pre-distortion algorithm to improve jitter tolerance. The line drivers reduce their drive level during the second half of "wide" Manchester pulses and maintain a full drive level during narrow pulses and the first half of the wide pulses. This reduces jitter caused by overcharging the line.
6.2.3
10BASE-T Receive Blocks
The PHY unit performs Manchester decoding and timing recovery when in 10 Mbps mode. The Manchester-encoded data stream is decoded from the RD pair to separate Receive Clock and Receive Data from the differential signal. This data is transferred to the CSMA unit at 2.5 MHz/ nibble. In 10 Mbps mode, data is expected to be received on the receive differential pair after passing through isolation transformers. The input differential voltage range capability for the Twisted Pair Ethernet (TPE) receiver is greater than 585 mV and less than 3.1 V. The TPE receive buffer distinguishes valid receive data, link test pulses, and idles, according to the requirements of the 10BASE-T standard. In 10 Mbps mode, the PHY unit can detect errors in the receive data, including voltage drops prior to the end-of-frame bit. Collision detection in 10 Mbps mode is initiated by simultaneous transmission and reception. If the PHY unit detects this condition, it asserts a collision indication to the CSMA/CD unit.
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6.2.4
10BASE-T Link Integrity and Full Duplex
The link integrity in 10 Mbps works with link pulses. The PHY unit senses and differentiates those link pulses from fast link pulses and from 100BASE-TX idles. The link beat pulse is also used to determine if the receive pair polarity is reversed. If it is, the polarity is corrected internally. The PHY unit supports 10 Mbps full duplex by disabling the collision function, the squelch test, and the carrier sense transmit function. This allows the PHY unit to transmit and receive simultaneously, achieving up to 20 Mbps network bandwidth using Auto-Negotiation. Full duplex can only be used in point-to-point connections (no shared media).
6.3
Auto-Negotiation
The PHY unit supports Auto-Negotiation, which is an automatic configuration scheme designed to manage interoperability in multifunctional LAN environments. An Auto-Negotiation capable device can detect and automatically configure its port to take maximum advantage of common modes of operation without user intervention or prior knowledge by either station. AutoNegotiation is described in IEEE Standard 802.3u, clause 28.
6.3.1
Description
A PHY's capability is encoded by bursts of link pulses called Fast Link Pulses (FLPs). Connection is established by FLP exchange and handshake during link initialization time. After the link is established by this handshake, the native link pulse scheme resumes. A reset or management renegotiate command (through the MDI interface) will restart the process. If the PHY unit cannot perform Auto-Negotiation, it will set this bit to 0 and determine the speed using Parallel Detection. The PHY unit supports four technologies: 100BASE-Tx Full and Half Duplex and 10BASE-T Full and Half Duplex. Since only one technology can be used at a time (after every re-negotiate command), a prioritization scheme is used to ensure that the ability of the highest common denominator is chosen.
6.3.2
Parallel Detect and Auto-Negotiation
The PHY unit can automatically determine the speed of the link by using Parallel Detect as an alternative to Auto-Negotiation. Upon a reset, a link status fail, or a negotiate/re-negotiate command, the PHY unit inserts a long delay during which no link pulses are transmitted. This period insures that the PHY unit`s link partner has gone into a Link Fail state before AutoNegotiation or Parallel Detection begins. The PHY unit will look for both FLPs and link integrity pulses. The following diagram illustrates this process.
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Figure 10. Auto-Negotiation and Parallel Detect
Force_Fail
Ability detect either by parallel detect or autonegotiation.
Parallel Detection Auto-Negotiation
10Base-T or 100Base-TX Link Ready
FLP capable
Look at Link Pulse; Auto-Negotiation capable = 0
Auto-Negotiation capable = 1 Ability Match
LINK PASS
Auto-Negotiation Complete bit set
6.4
LED Description
The PHY unit supports three LED pins to indicate link status, network activity and network speed. Each pin can source 10 mA.
* Link: This LED is off until a valid link has been detected. After a valid link has been detected,
the LED will remain on (active-low).
* Activity: This LED blinks on and off when activity is detected on the wire. * Speed: This LED will be on if a 100BASE-TX link is detected and off if a 10BASE-T link is
detected. If the link fails while in Auto-Negotiation, this LED will keep the last valid link state. If 100BASE-TX link is forced this LED will be on, regardless of the link status. This LED will be off if the 10BASE-T link is forced, regardless of the link status. MDI register 27 in Section 11.3.12, "Register 27: PHY Unit Special Control" details the information for LED function mapping and support enhancements. Figure 11 provides possible schematic diagrams for configurations using two and three LEDs.
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Figure 11. Two and Three LED Schematic Diagram
vcc
LILED# ACTLED# SPEEDLED#
R R
82551
LILED#
R R R
ACTLED# SPEEDLED#
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7.0
Configuration Registers
The 82551ER acts as both a master and a slave on the PCI bus. As a master, the 82551ER interacts with the system main memory to access data for transmission or deposit received data. As a slave, some 82551ER control structures are accessed by the host CPU to read or write information to the on-chip registers. The CPU also provides the 82551ER with the necessary commands and pointers that allow it to process receive and transmit data.
7.1
LAN (Ethernet) PCI Configuration Space
The 82551ER PCI configuration space is configured as 16 Dwords of Type 0 Configuration Space Header, as defined in the PCI Specification, Revision 2.1. A small section is also configured according to its device specific configuration space. The configuration space header is depicted below in Figure 12.
Figure 12. PCI Configuration Registers
Device ID Status Class Code BIST Header Type Latency Timer Vendor ID Command Revision ID Cache Line Size 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h Subsystem Vendor ID 2Ch 30h Cap_Ptr Reserved Max_Lat Min_Gnt Interrupt Pin Next Item Ptr Interrupt Line Capability ID 34h 38h 3Ch DCh E0h
CSR Memory Mapped Base Address Register CSR I/O Mapped Base Address Register Flash Memory Mapped Base Address Register Reserved Base Address Register Reserved Base Address Register Reserved Base Address Register Reserved (PCI mode) Subsystem ID
Expansion ROM Base Address Register Reserved
Power Management Capabilities Reserved Data
Power Management CSR
7.1.1
PCI Vendor ID and Device ID Registers
The Vendor ID and Device ID of the 82551ER are both read only word entities. Their values are: Vendor ID: 8086h Device ID: 1209h
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7.1.2
PCI Command Register
The 82551ER Command register at word address 04h in the PCI configuration space provides control over the 82551ER's ability to generate and respond to PCI cycles. If a 0 is written to this register, the 82551ER is logically disconnected from the PCI bus for all accesses except configuration accesses. The format of this register is shown in the figure below.
Figure 13. PCI Command Register
15 10 9 8 7 6 5 4 3 2 1 0
Reserved
0
0
0
0
SERR# Enable Parity Error Response Memory Write and Invalidate Enable Bus Master Enable Memory Space IO space
Note: Bits three, five, seven, and nine are set to 0b. The table below describes the bits of the PCI Command register.
Table 13. PCI Command Register Bits
Bits Name Description
15:10
Reserved
These bits are reserved and should be set to 000000b. This bit controls a device's ability to enable the SERR# driver. A value of 0b disables the SERR# driver. A value of 1b enables the SERR# driver. This bit must be set to report address parity errors. In the 82551ER, this bit is configurable and has a default value of 0b. This bit controls a device's response to parity errors. A value of 0b causes the device to ignore any parity errors that it detects and continue normal operation. A value of 1b causes the device to take normal action when a parity error is detected. This bit must be set to 0b after RST# is asserted. In the 82551ER, this bit is configurable and has a default value of 0b. This bit controls a device's ability to use the Memory Write and Invalidate command. A value of 0b disables the device from using the Memory Write and Invalidate Enable command. A value of 1b enables the device to use the Memory Write and Invalidate command. In the 82551ER, this bit is configurable and has a default value of 0b. This bit controls a device's ability to act as a master on the PCI bus. A value of 0b disables the device from generating PCI accesses. A value of 1b allows the device to behave as a bus master. In the 82551ER, this bit is configurable and has a default value of 0b. This bit controls a device's response to the memory space accesses. A value of 0b disables the device response. A value of 1b allows the device to respond to memory space accesses. In the 82551ER, this bit is configurable and its default value of 0b. This bit controls a device's response to the I/O space accesses. A value of 0b disables the device response. A value of 1b allows the device to respond to I/O space accesses. In the 82551ER, this bit is configurable and the default value of 0b.
8
SERR# Enable
6
Parity Error Control
4
Memory Write and Invalidate Enable
2
Bus Master
1
Memory Space
0
I/O Space
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7.1.3
PCI Status Register
The 82551ER Status register is used to record status information for PCI bus related events. The format of this register is shown in the figure below.
Figure 14. PCI Status Register
31 30 29 28 27 26 25 24 23 22 21 20 19 16
000 1
Detected Parity Error Signaled System Error Received Master Abort Received Target Abort Signaled Target Abort Devsel Timing Parity Error Detected Fast Back To Back (target) Capabilities List
1001
Reserved
Note:
Bits 21, 22, 26, and 27 are set to 0b and bits 20, 23, and 25 are set to 1b. The PCI Status register bits are described in the table below.
Table 14. PCI Status Register Bits
Bits Name Description
31
Detected Parity Error
This bit indicates whether a parity error is detected. This bit must be set by the device when it detects a parity error, even if parity error handling is disabled (as controlled by the Parity Error Response bit in the PCI Command register, bit 6). In the 82551ER, the initial value of the Detected Parity Error bit is 0b. This bit is set until cleared by writing a 1b. This bit indicates when the device has asserted SERR#. In the 82551ER, the initial value of the Signaled System Error bit is 0b. This bit is set until cleared by writing a 1b. This bit indicates whether or not a master abort has occurred. This bit must be set by the master device when its transaction is terminated with a master abort. In the 82551ER, the initial value of the Received Master Abort bit is 0b. This bit is set until cleared by writing a 1b. This bit indicates that the master has received the target abort. This bit must be set by the master device when its transaction is terminated by a target abort. In the 82551ER, the initial value of the Received Target Abort bit is 0b. This bit is set until cleared by writing a 1b. This bit indicates whether a transaction was terminated by a target abort. This bit must be set by the target device when it terminates a transaction with target abort. In the 82551ER, this bit is always set to 0b. These two bits indicate the timing of DEVSEL#: 00b - Fast 01b - Medium 10b - Slow 11b - Reserved In the 82551ER, these bits are always set to 01b, medium.
30
Signaled System Error
29
Received Master Abort
28
Received Target Abort
27
Signaled Target Abort
26:25
DEVSEL# Timing
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Table 14. PCI Status Register Bits
Bits Name Description
This bit indicates whether a parity error has been detected. This bit is set to 1b when the following three conditions are met: 1. The bus agent asserted PERR# itself or observed PERR# asserted. 24 Parity Error Detected 2. The agent setting the bit acted as the bus master for the operation in which the error occurred. 3. The Parity Error Response bit in the command register (bit 6) is set. In the 82551ER, the initial value of the Parity Error Detected bit is 0b. This bit is set until cleared by writing a 1b. This bit indicates a device's ability to accept fast back-to-back transactions when the transactions are not to the same agent. A value of 0b disables fast back-to-back ability. A value of 1b enables fast back-to-back ability. In the 82551ER, this bit is read only and is set to 1b. This bit indicates whether the 82551ER implements a list of new capabilities such as PCI Power Management. A value of 0b means that this function does not implement the Capabilities List. If this bit is set to 1b, the Cap_Ptr register provides an offset into the 82551ER PCI Configuration space pointing to the location of the first item in the Capabilities List. This bit is set only if the power management bit in the EEPROM is set. These bits are reserved and should be set to 0000b.
23
Fast Back-to-Back
20
Capabilities List
19:16
Reserved
7.1.4
PCI Revision ID Register
The Revision ID is an 8-bit read only register. The three least significant bits of the Revision ID can be overridden by the ID and Revision ID fields in the EEPROM (Section 5.7, "Serial EEPROM Interface"). The default values of the Revision ID are: 82551ER (A-step): 0Fh
7.1.5
PCI Class Code Register
The Class Code register is read only and is used to identify the generic function of the device and, in some cases, specific register level programming interface. The register is broken into three byte size fields. The upper byte is a base class code and specifies the 82551ER as a network controller, 2h. The middle byte is a subclass code and specifies the 82551ER as an Ethernet controller, 0h. The lower byte identifies a specific register level programming interface and the 82551ER always returns a 0h in this field.
7.1.6
PCI Cache Line Size Register
In order for the 82551ER to support the Memory Write and Invalidate (MWI) command, the 82551ER must also support the Cache Line Size (CLS) register in PCI Configuration space. The register supports only cache line sizes of 8 and 16 Dwords. Any value other than 8 or 16 that is written to the register is ignored and the 82551ER does not use the MWI command. If a value other than 8 or 16 is written into the CLS register, the 82551ER returns all zeroes when the CLS register is read. The figure below illustrates the format of this register. Figure 15. Cache Line Size Register
7 6 5 4 3 2 1 0
0
0
0
RW
RW
0
0
0
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Note:
Bit 3 is set to 1b only if the value 00001000b (8h) is written to this register, and bit 4 is set to 1b only if the value of 00010000b (16h) is written to this register. All other bits are read only and will return a value of 0b on read. The BIOS is expected to write to this register. Therefore, the 82551ER driver should not write to it.
7.1.7
PCI Latency Timer
The Latency Timer register is a byte wide register. When the 82551ER is acting as a bus master, this register defines the amount of time, in PCI clock cycles, that it may own the bus.
7.1.8
PCI Header Type
The Header Type register is a byte read only register. It is equal to 00h for a single function Ethernet card and 80h for a combination Ethernet and modem card. The value of the header type is set by the EEPROM (Section 5.7, "Serial EEPROM Interface"). In a dual function card, the OS will read the next configuration registers bank at offset 100h.
7.1.9
PCI Base Address Registers
One of the most important functions for enabling superior configurability and ease of use is the ability to relocate PCI devices in address spaces. The 82551ER contains three types of Base Address Registers (BARs). Two are used for memory mapped resources, and one is used for I/O mapping. Each register is 32 bits wide. The least significant bit in the BAR determines whether it represents a memory or I/O space. The figures below show the layout of a BAR for both memory and I/O mapping. After determining this information, power-up software can map the memory and I/O controllers into available locations and proceed with system boot. In order to do this mapping in a device independent manner, the base registers for this mapping are placed in the predefined header portion of configuration space. Device drivers can then access this configuration space to determine the mapping of a particular device.
Figure 16. Base Address Register for Memory Mapping 31 Base Address
Prefetchable The prefetchable bit is set to `0' in 82551QM devices Type 00 - locate anywhere in 32-bit address space 01 - locate below 1 Mbyte 10 - locate anywhere in 64-bit address space 11 - reserved Memory space indicator
43210 0
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Figure 17. Base Address Register for I/O Mapping 31 Base Address
Reserved I/O space indicator
210 01
Note:
Bit 0 in all base registers is read only and used to determine whether the register maps into memory or I/O space. Base registers that map to memory space must return a 0b in bit 0. Base registers that map to I/O space must return 1b in bit 0. Base registers that map into I/O space are always 32 bits wide with bit 0 hard-wired to a 1b, bit 1 is reserved and must return 0b on reads, and the other bits are used to map the device into I/O space. The number of upper bits that a device actually implements depends on how much of the address space the device will respond to. For example, a device that wants a 1 Mbyte memory address space would set the most significant 12 bits of the base address register to be configurable, setting the other bits to 0b. The 82551ER contains BARs for the Control/Status Register (CSR), Flash, and Expansion ROM.
7.1.9.1
CSR Memory Mapped Base Address Register
The 82551ER requires one BAR for memory mapping. Software determines which BAR, memory or I/O, is used to access the 82551ER CSR registers. The memory space for the 82551ER CSR Memory Mapped BAR is 4 Kbytes. The space is marked as not prefetchable and is mapped anywhere in the 32-bit memory address space.
7.1.9.2
CSR I/O Mapped Base Address Register
The 82551ER requires one BAR for I/O mapping. Software determines which BAR, I/O or memory, is used to access the 82551ER CSR registers. The I/O space for the 82551ER CSR I/O BAR is 64 bytes.
7.1.9.3
Flash Memory Mapped Base Address Register
The Flash Memory BAR is a Dword register. The 82551ER physically supports a 128 Kbyte Flash device.
7.1.9.4
Expansion ROM Base Address Register
The Expansion ROM has a memory space of 1 Mbyte and its BAR is a Dword register that supports a 128 Kbyte memory via the 82551ER local bus. The Expansion ROM BAR can be disabled by setting the Boot Disable bit located in the EEPROM (word Ah, bit 11). If the Boot Disable bit is set, the 82551ER returns a 0b for all bits in this address register, avoiding request of memory allocation for this space.
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7.1.10
Base Address Registry Summary
The preceding description of the Base Address Registers' functions are summarized in the following table: Table 15. Base Address Register Functions
Register Name PCI Function PCI Window
BAR0 BAR1 BAR2 Expansion BAR
Memory CSR I/O CSR Flash BootROM
4 Kbytes 4 Kbytes 128 Kbytes 1 Mbyte
7.1.11
PCI Subsystem Vendor ID and Subsystem ID Registers
The Subsystem Vendor ID field identifies the vendor of an 82551ER based solution. The Subsystem Vendor ID values are based upon the vendor's PCI Vendor ID and is controlled by the PCI Special Interest Group (SIG). The Subsystem ID field identifies the 82551ER based specific solution implemented by the vendor indicated in the Subsystem Vendor ID field. The 82551ER provides support for configurable Subsystem Vendor ID and Subsystem ID fields. After hardware reset is de-asserted, the 82551ER automatically reads addresses Ah through Ch of the EEPROM. The first of these 16-bit values is used for controlling various 82551ER functions. The second is the Subsystem ID value, and the third is the Subsystem Vendor ID value. Again, the default values for the Subsystem ID and Subsystem Vendor ID are 0h and 0h, respectively. The 82551ER checks bit numbers 15, 14, and 13 in the EEPROM, word Ah and functions according to Table 16 below.
Table 16. ID Fields Programming
Signature (Bits 15:14) ID (Bit 13) AltID (Bit 7) Device ID Vendor ID Revision IDa (A-0 and A-1) Subsystem ID Subsystem Vendor ID
11bb, 10b, 00b 01b 01b 01b
X 1b 0b 0b
X X 0b 0b
1209h 1209h 1209h 1209h
8086h 8086h 8086h 8086h
0Fh Word Ah, bits 10:8 0Fh 08h
0000h Word Bh Word Bh Word Bh
0000h Word Ch Word Ch Word Ch
a. The Revision ID is subject to change according to the silicon stepping. b. If bit 15 equals 1b, the EEPROM is invalid and the default values are used.
The above table implies that if the 82551ER detects the presence of an EEPROM (as indicated by a value of 01b in bits 15 and 14), then bit number 13 determines whether the values read from the EEPROM, words Bh and Ch, are loaded into the Subsystem ID (word Bh) and Subsystem Vendor ID (word Ch) fields. If bits 15 and 14 equal 01b and bit 13 equals 1b, the three least significant bits of the Revision ID field are programmed by bits 10:8 of the first EEPROM word, Ah.
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Between the de-assertion of reset and the completion of the automatic EEPROM read, the 82551ER does not respond to any PCI configuration cycles. If the 82551ER happens to be accessed during this time, it will Retry the access. More information on Retry is provided in Section 5.2.1.1.3, "Retry Premature Accesses".
7.1.12
Capability Pointer
The Capability Pointer is a hard-coded byte register with a value of DCh. It provides an offset within the Configuration Space for the location of the Power Management registers.
7.1.13
Interrupt Line Register
The Interrupt Line register identifies which system interrupt request line on the interrupt controller the device's PCI interrupt request pin (as defined in the Interrupt Pin register) is routed to.
7.1.14
Interrupt Pin Register
The Interrupt Pin register is read only and defines which of the four PCI interrupt request pins, INTA# through INTD#, a PCI device is connected to. The 82551ER is connected the INTA# pin.
7.1.15
Minimum Grant Register
The Minimum Grant (Min_Gnt) register is an optional read only register for bus masters and is not applicable to non-master devices. It defines the amount of time the bus master wants to retain PCI bus ownership when it initiates a transaction. The default value of this register for the 82551ER is 08h.
7.1.16
Maximum Latency Register
The Maximum Latency (Max_Lat) register is an optional read only register for bus masters and is not applicable to non-master devices. This register defines how often a device needs to access the PCI bus. The default value of this register for the 82551ER is 18h.
7.1.17
Capability ID Register
The Capability ID is a byte register. It signifies whether the current item in the linked list is the register defined for PCI Power Management. PCI Power Management has been assigned the value of 01h. The 82551ER is fully compliant with the PCI Power Management Specification, Revision 2.2.
7.1.18
Next Item Pointer
The Next Item Pointer is a byte register. It describes the location of the next item in the 82551ER's capability list. Since power management is the last item in the list, this register is set to 0b.
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7.1.19
Power Management Capabilities Register
The Power Management Capabilities register is a word read only register. It provides information on the capabilities of the 82551ER related to power management. The 82551ER reports a value of FE21h if it is connected to an auxiliary power source and 7E21h otherwise. It indicates that the 82551ER supports wake-up in the D3 state if power is supplied, either Vcc or VAUX.
Table 17. Power Management Capability Register
Bits Default Read/Write Description PME Support. This five-bit field indicates the power states in which the 82551ER may assert PME#. The 82551ER supports wake-up in all power states if it is fed by an auxiliary power supply (VAUX) and D0, D1, D2, and D3hot if it is fed by PCI power. D2 Support. If this bit is set, the 82551ER supports the D2 power state. D1 Support. If this bit is set, the 82551ER supports the D1 power state. Auxiliary Current. This field reports whether the 82551ER implements the Data registers. The auxiliary power consumption is the same as the current consumption reported in the D3 state in the Data register. Device Specific Initialization (DSI). The DSI bit indicates whether special initialization of this function is required (beyond the standard PCI configuration header) before the generic class device driver is able to use it. DSI is required for the 82551ER after D3-to-D0 reset. Reserved (PCI) PME Clock. The 82551ER does not require a clock to generate a power management event. Version. A value of 010b indicates that the 82551ER complies with of the PCI Power Management Specification, Revision 2.2.
31:27
00011b (no VAUX) 11111b (VAUX) 1b 1b
Read Only
26 25
Read Only Read Only
24:22
000b
Read Only
21
1b
Read Only
20 19 18:16
0b (PCI)
Read Only Read Only Read Only
0b 010b
7.1.20
Power Management Control/Status Register (PMCSR)
The Power Management Control/Status is a word register. It is used to determine and change the current power state of the 82551ER and control the power management interrupts in a standard manner.
Table 18. Power Management Control and Status Register
Bits Default Read/Write Description PME Status. This bit is set upon a wake-up event. It is independent of the state of the PME Enable bit. If 1b is written to this bit, the bit will be cleared. It also de-asserts the PME# signal and clears the PME status bit in the Power Management Driver Register. When the PME# signal is enabled, the PME# signal reflects the state of the PME status bit. Data Scale. This field indicates the data register scaling factor. It equals 10b for registers zero through eight and 00b for registers nine through fifteen. Data Select. This field is used to select which data is reported through the Data register and Data Scale field.
15
0b
Read/Clear
14:13
00b
Read Only
12:9
0000b
Read Only
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Table 18. Power Management Control and Status Register
Bits Default Read/Write Description PME Enable. This bit enables the 82551ER to assert PME#. Reserved. These bits are reserved and should be set to 000b. Dynamic Data. The 82551ER does not support the ability to monitor the power consumption dynamically. Reserved. These bits are reserved and should be set to 00b. Power State. This 2-bit field is used to determine the current power state of the 82551ER and to set the 82551ER into a new power state. The definition of the field values is as follows.
8 7:5 4 3:2
0b 000b 0b 00b
Read Clear Read Only Read Only Read Only
1:0
00b
Read/Write
00 - D0 01 - D1 10 - D2 11 - D3
7.1.21
Data Register
The data register is an 8-bit read only register that provides a mechanism for the 82551ER to report state dependent maximum power consumption and heat dissipation. The value reported in this register depends on the value written to the Data Select field in the PMCSR register. The power measurements defined in this register have a dynamic range of 0 to 2.55 W with 0.01 W resolution according to the Data Scale. The value in this register is hard-coded in the silicon. The structure of the data register is presented below. Table 19. Ethernet Data Register
Data Select Data Scale Data Reported
0 1 2 3 4 5 6 7 8 9-15
2 2 2 2 2 2 2 2 2 0
D0 Power Consumption = 60 (600 mW) D1 Power Consumption = 42 (420 mW) D2 Power Consumption = 42 (420 mW) D3 Power Consumption = 42 (420 mW) D0 Power Dissipated = 60 (60 mW) D1 Power Dissipated = 42 (420 mW) D2 Power Dissipated = 42 (420 mW) D3 Power Dissipated = 42 (420 mW) Common Function Power Dissipated = 00 Reserved (00h)
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8.0
8.1
Control/Status Registers
LAN (Ethernet) Control/Status Registers
The 82551ER's Control/Status Register (CSR) is illustrated in the figure below.
Figure 18. Control/Status Register
D31 Upper Word D16 D15 Lower Word D0 Offset
SCB Command Word
SCB Status Word
00h 04h 08h
System Control Block General Pointer PORT EEPROM Control Register Flash Control Register
0Ch 10h 14h
Management Data Interface (MDI) Control Register Receive Direct Memory Access Byte Count PMDR Reserved Flow Control Register General Status Reserved Command Block Pointer Reserved Reserved Function Event Register Function Event Mask Register Function Present State Register Force Event Register Reserved General Control
18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch
NOTE: In Figure 18 above, SCB is defined as the System Control Block of the 82551ER, and PMDR is defined as the Power Management Driver Register.
SCB Status Word: The 82551ER places the status of its Command and Receive units and interrupt indications in this register for the CPU to read. SCB Command Word: The CPU places commands for the Command and Receive units in this register. Interrupts are also acknowledged in this register. SCB General Pointer: The SCB General Pointer register points to various data structures in main memory depending on the current SCB Command word. PORT Interface: The PORT interface allows the CPU to reset the 82551ER, force the 82551ER to dump information to main memory, or perform an internal self test. Flash Control Register: The Flash Control register allows the CPU to enable writes to an external Flash. EEPROM Control Register: The EEPROM Control register allows the CPU to read and write to an external EEPROM.
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MDI Control Register: The MDI Control register allows the CPU to read and write information from the PHY unit (or an external PHY component) through the Management Data Interface. Receive DMA Byte Count: The Receive DMA Byte Count register keeps track of how many bytes of receive data have been passed into host memory via DMA. Flow Control Register: This register holds the flow control threshold value and indicates the flow control commands to the 82551ER. PMDR: The Power Management Driver Register provides an indication in memory and I/O space that a wake-up interrupt has occurred. General Control: The General Control register allows the 82551ER to enter the deep power-down state and provides the ability to disable the Clockrun functionality. General Status: The General Status register describes the status of the 82551ER's duplex mode, speed, and link. Function Event Mask: The Function Event Mask register masks the CSTSCHG signal assertion for specified events. Function Present State: The Function Present State register reflects the current state of each condition that may cause a status change or interrupt. Force Event: The Force Event register simulates the status change events for troubleshooting purposes.
8.1.1
System Control Block Status Word
The System Control Block (SCB) Status Word contains status information relating to the 82551ER's Command and Receive units.
Table 20. System Control Block Status Word
Bits Name Description Command Unit (CU) Executed. The CX bit indicates that the CU has completed executing a command with its interrupt bit set. Frame Received. The FR bit indicates that the Receive Unit (RU) has finished receiving a frame. CU Not Active. The CNA bit is set when the CU is no longer active and in either an idle or suspended state. Receive Not Ready. The RNR bit is set when the RU is not in the ready state. This may be caused by an RU Abort command, a no resources situation, or set suspend bit due to a filled Receive Frame Descriptor. Management Data Interrupt. The MDI bit is set when a Management Data Interface read or write cycle has completed. The management data interrupt is enabled through the interrupt enable bit (bit 29 in the Management Data Interface Control register in the CSR). Software Interrupt. The SWI bit is set when software generates an interrupt.
15 14 13
CX FR CNA
12
RNR
11
MDI
10 9 8
SWI Reserved FCP
This bit is reserved and should be set to 0b.
Flow Control Pause. The FCP bit is used as the flow control pause bit.
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Table 20. System Control Block Status Word
Bits Name Description Command Unit Status. The CUS field contains the status of the Command Unit. Receive Unit Status. The RUS field contains the status of the Receive Unit.
7:6 5:2 1:0
CUS RUS Reserved
These bits are reserved and should be set to 00b.
8.1.2
System Control Block Command Word
Commands for the 82551ER's Command and Receive units are placed in this register by the CPU.
Table 21. System Control Block Command Word
Bits Name Description Specific Interrupt Mask. Setting this bit to 1b causes the 82551ER to stop generating an interrupt (in other words, de-assert the INTA# signal) on the corresponding event. Software Generated Interrupt. Setting this bit to 1b causes the 82551ER to generate an interrupt. Writing a 0b to this bit has no effect. Interrupt Mask. If the Interrupt Mask bit is set to 1b, the 82551ER will not assert its INTA# pin. The M bit has higher precedence that the Specific Interrupt Mask bits and the SI bit. Command Unit Command. This field contains the CU command. Receive Unit Command. This field contains the RU command.
31:26
Specific Interrupt Mask SI
25
24 23:20 19:16
M CUC RUC
8.1.3
System Control Block General Pointer
The System Control Block (SCB) General Pointer is a 32-bit field that points to various data structures depending on the command in the CU Command or RU Command field.
8.1.4
PORT
The PORT interface allows software to perform certain control functions on the 82551ER. This field is 32 bits wide:
* Address and Data (bits 32:4) * PORT Function Selection (bits 3:0)
The 82551ER supports four PORT commands: Software Reset, Self-test, Selective Reset, and Dump.
8.1.5
Flash Control Register
The Flash Control Register is a 32-bit field that allows access to an external Flash device.
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8.1.6
EEPROM Control Register
The EEPROM Control Register is a 32-bit field that enables a read from and a write to the external EEPROM.
8.1.7
Management Data Interface Control Register
The Management Data Interface (MDI) Control register is a 32-bit field and is used to read and write bits from the MDI.
Table 22. MDI Control Register
Bits Description
31:30 29 28 27:26 25:21 20:16 15:0
These bits are reserved and should be set to 00b.
Interrupt Enable. When this bit is set to 1b by software, the 82551ER asserts an interrupt to indicate the end of an MDI cycle. Ready. This bit is set to 1b by the 82551ER at the end of an MDI transaction. Software should set this bit to 0 at the same time the command is written. Opcode. These bits define the opcode: 01 for MDI write and 10 for MDI read. All other values (00 and 11) are reserved. PHY Address. This field of bits contains the PHY address. PHY Register Address. This field of bits contains the PHY Register Address. Data. In a write command, software places the data bits in this field, and the 82551ER transfers the data to the PHY unit. During a read command, the 82551ER reads these bits serially from the PHY unit, and software reads the data from this location.
8.1.8
Receive Direct Memory Access Byte Count
The Receive DMA Byte Count register keeps track of how many bytes of receive data have been passed into host memory via DMA.
8.1.9
Flow Control Register
The Flow Control Register contains the following fields:
* Flow Control Command
The Flow Control Command field describes the action of the flow control process (for example, pause, on, or off).
* Flow Control Threshold
The Flow Control Threshold field contains the threshold value (in other words, the number of free bytes in the Receive FIFO).
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8.1.10
General Control Register
The General Control register is a byte register and is described below. The General Control register is used in CardBus mode only.
Table 23. General Control Register
Bits Default Read/Write Description Reserved. These bits are reserved and should be set to 000000b. Deep Power-Down on Link Down Enable. If a 1b is written to this field, the may enter a deep power-down state (sub-3 mA) in the D2 and D3 power states while the link is down.
7:2
000000b
Read Only
1
0b
Read/Write
In this state, the does not keep link integrity. This state is not supported for point-to-point connection of two end stations.
Clockrun Signal Disable. If this bit is set to 1b, then the always requests the PCI clock signal. This mode can be used to overcome potential receive overruns caused by Clockrun signal latencies over 5 s.
0
0b
Read/Write
8.1.11
General Status Register
The General Status register is used in CardBus mode only and is a byte register that indicates the link status of the 82551QM.
Table 24. General Status Register
Bits Default Read/Write Description Reserved. These bits are reserved and should be set to 00000b. Duplex Mode. This bit indicates the wire duplex mode: full duplex (1b) or half duplex (0b). Speed. This bit indicates the wire speed: 100 Mbps (1b) or 10 Mbps (0b). Link Status Indication. This bit indicates the status of the link: valid (1b) or invalid (0b).
7:3 2 1 0
00000b --0b
Read Only Read Only Read Only Read Only
8.2
Statistical Counters
The 82551ER provides information for network management statistics by providing on-chip statistical counters that count a variety of events associated with both transmit and receive. The counters are updated by the 82551ER when it completes the processing of a frame (that is, when it
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82551ER -- Networking Silicon
has completed transmitting a frame on the link or when it has completed receiving a frame). The Statistical Counters are reported to the software on demand by issuing the Dump Statistical Counters command or Dump and Reset Statistical Counters command in the SCB Command Unit Command (CUC) field. Table 25. Statistical Counters
ID Counter Description
0
Transmit Good Frames
This counter contains the number of frames that were transmitted properly on the link. It is updated only after the actual transmission on the link is completed, not when the frame was read from memory, as is done for the Transmit Command Block status. This counter contains the number of frames that were not transmitted because they encountered the configured maximum number of collisions. This counter contains the number of frames that were not transmitted due to an encountered collision after the configured slot time. A transmit underrun occurs because the system bus cannot keep up with the transmission. This counter contains the number of frames that were either not transmitted or retransmitted due to a transmit DMA underrun. If the 82551ER is configured to retransmit on underrun, this counter may be updated multiple times for a single frame. This counter contains the number of frames that were transmitted by the 82551ER despite the fact that it detected the de-assertion of CRS during the transmission. This counter contains the number of frames that were deferred before transmission due to activity on the link. This counter contains the number of transmitted frames that encountered one collision. This counter contains the number of transmitted frames that encountered more than one collision. This counter contains the total number of collisions that were encountered while attempting to transmit. This count includes late collisions and frames that encountered MAXCOL. This counter contains the number of frames that were received properly from the link. It is updated only after the actual reception from the link is completed and all the data bytes are stored in memory. This counter contains the number of aligned frames discarded because of a CRC error. This counter is updated, if needed, regardless of the Receive Unit state. The Receive CRC Errors counter is mutually exclusive of the Receive Alignment Errors and Receive Short Frame Errors counters. This counter contains the number of frames that are both misaligned (for example, CRS de-asserts on a non-octal boundary) and contain a CRC error. The counter is updated, if needed, regardless of the Receive Unit state. The Receive Alignment Errors counter is mutually exclusive of the Receive CRC Errors and Receive Short Frame Errors counters.
4
Transmit Maximum Collisions (MAXCOL) Errors Transmit Late Collisions (LATECOL) Errors
8
12
Transmit Underrun Errors
16
Transmit Lost Carrier Sense (CRS)
20 24 28
Transmit Deferred Transmit Single Collisions Transmit Multiple Collisions
32
Transmit Total Collisions
36
Receive Good Frames
40
Receive CRC Errors
44
Receive Alignment Errors
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Table 25. Statistical Counters
ID Counter Description
48
Receive Resource Errors
This counter contains the number of good frames discarded due to unavailability of resources. Frames intended for a host whose Receive Unit is in the No Resources state fall into this category. If the 82551ER is configured to Save Bad Frames and the status of the received frame indicates that it is a bad frame, the Receive Resource Errors counter is not updated. This counter contains the number of frames known to be lost because the local system bus was not available. If the traffic problem persists for more than one frame, the frames that follow the first are also lost; however, because there is no lost frame indicator, they are not counted. This counter contains the number of frames that encountered collisions during frame reception. This counter contains the number of received frames that are shorter than the minimum frame length. The Receive Short Frame Errors counter is mutually exclusive to the Receive Alignment Errors and Receive CRC Errors counters. A short frame will always increment only the Receive Short Frame Errors counter. This counter contains the number of Flow Control frames transmitted by the 82551ER. This count includes both the Xoff frames transmitted and Xon (PAUSE(0)) frames transmitted. This counter contains the number of Flow Control frames received by the 82551ER. This count includes both the Xoff frames received and Xon (PAUSE(0)) frames received. This counter contains the number of MAC Control frames received by the 82551ER that are not Flow Control Pause frames. These frames are valid MAC control frames that have the predefined MAC control Type value and a valid address but has an unsupported opcode.
52
Receive Overrun Errors
56
Receive Collision Detect (CDT)
60
Receive Short Frame Errors
64
Flow Control Transmit Pause
68
Flow Control Receive Pause
72
Flow Control Receive Unsupported
The Statistical Counters are initially set to zero by the 82551ER after reset. They cannot be preset to anything other than zero. The 82551ER increments the counters by internally reading them, incrementing them and writing them back. This process is invisible to the CPU and PCI bus. In addition, the counters adhere to the following rules:
* The counters are wrap-around counters. After reaching FFFFFFFFh the counters wrap around
to 0.
* The 82551ER updates the required counters for each frame. It is possible for more than one
counter to be updated as multiple errors can occur in a single frame.
* The counters are 32 bits wide and their behavior is fully compatible with the IEEE 802.1
standard. The 82551ER supports all mandatory and recommend statistics functions through the status of the receive header and directly through these Statistical Counters. The CPU can access the counters by issuing a Dump Statistical Counters SCB command. This provides a "snapshot", in main memory, of the internal 82551ER statistical counters. The 82551ER supports 19 counters. The dump could consist of either 16 or 19 counters, depending on the status of the Extended Statistics Counters configuration bits in the Configuration command.
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82551ER -- Networking Silicon
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Datasheet
Networking Silicon -- 82551ER
9.0
PHY Unit Registers
The 82551ER provides status and accepts management information via the Management Data Interface (MDI) within the CSR space. Acronyms mentioned in the registers are defined as follows: SC RO ELL LH self cleared read only EEPROM setting affects content latch low latch high
9.1
9.1.1
MDI Registers 0 - 7
Register 0: Control Register
Table 26. Register 0: Control
Bit(s) Name Description Default R/W
15
Reset
This bit sets the status and control register of the PHY to their default states and is self-clearing. The PHY returns a value of one until the reset process has completed and accepts a read or write transaction. 1 = PHY Reset This bit enables loopback of transmit data nibbles from the TXD[3:0] signals to the receive data path. The PHY unit's receive circuitry is isolated from the network. Note that this may cause the descrambler to lose synchronization and produce 560 nanoseconds of "dead time." Note also that the loopback configuration bit takes priority over the Loopback MDI bit. 1 = Loopback enabled 0 = Loopback disabled (Normal operation)
0
RW SC
14
Loopback
0
RW
13
Speed Selection
This bit controls speed when Auto-Negotiation is disabled and is valid on read when Auto-Negotiation is disabled. 1 = 100 Mbps 0 = 10 Mbps
1
RW
12
Auto-Negotiation Enable
This bit enables Auto-Negotiation. Bits 13 and 8, Speed Selection and Duplex Mode, respectively, are ignored when Auto-Negotiation is enabled. 1 = Auto-Negotiation enabled 0 = Auto-Negotiation disabled
1
RW
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82551ER -- Networking Silicon
Table 26. Register 0: Control
Bit(s) Name Description Default R/W
11
Power-Down
This bit sets the PHY unit into a low power mode. In low power mode, the PHY unit consumes no more than 30 mA. 1 = Power-Down enabled 0 = Power-Down disabled (Normal operation)
0
RW
10 9
Reserved Restart AutoNegotiation Duplex Mode
This bit is reserved and should be set to 0b. This bit restarts the Auto-Negotiation process and is selfclearing. 1 = Restart Auto-Negotiation process This bit controls the duplex mode when Auto-Negotiation is disabled. If the PHY reports that it is only able to operate in one duplex mode, the value of this bit shall correspond to the mode which the PHY can operate. When the PHY is placed in Loopback mode, the behavior of the PHY shall not be affected by the status of this bit, bit 8. 1 = Full Duplex 0 = Half Duplex
0 0
RW RW SC
8
0
RW
7
Collision Test
This bit will force a collision in response to the assertion of the transmit enable signal. 1 = Force COL 0 = Do not force COL
0
RW
6:0
Reserved
These bits are reserved and should be set to 0000000b.
0
RW
9.1.2
Register 1: Status Register
Table 27. Register 1: Status
Bit(s) Name Description Default R/W
15 14 13 12 11 10:7 6
Reserved 100BASE-TX Full Duplex 100 Mbps Half Duplex 10 Mbps Full Duplex 10 Mbps Half Duplex Reserved Management Frames Preamble Suppression Auto-Negotiation Complete Remote Fault
This bit is reserved and should be set to 0b. 1 = PHY able to perform full duplex 100BASE-TX 1 = PHY able to perform half duplex 100BASE-TX 1 = PHY able to operate at 10Mbps in full duplex mode 1 = PHY able to operate at 10 Mbps in half duplex mode These bits are reserved and should be set to 0000b. 0 = PHY will not accept management frames with preamble suppressed 1 = Auto-Negotiation process completed 0 = Auto-Negotiation process has not completed 0 = No remote fault condition detected
0 1 1 1 1 0 0
RO E RO RO RO RO RO RO
5 4
0 0
RO RO
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Networking Silicon -- 82551ER
Table 27. Register 1: Status
Bit(s) Name Description Default R/W
3 2 1 0
Auto-Negotiation Ability Link Status Jabber Detect Extended Capability
1 = PHY is able to perform Auto-Negotiation 1 = Valid link has been established 0 = Invalid link detected 1 = Jabber condition detected 0 = No jabber condition detected 1 = Extended register capabilities enabled
1 0 0 1
RO RO LL RO LH RO
9.1.3
Register 2: PHY Identifier Register
Table 28. Register 2: PHY Identifier
Bit(s) Name Description Default R/W
15:0
PHY ID (high byte)
Value: 02A8h
--
RO
9.1.4
Register 3: PHY Identifier Register
Table 29. Register 3 PHY Identifer
Bit(s) Name Description Default R/W
15:0
PHY ID (low byte)
Value: 0154h
--
RO
9.1.5
Register 4: Auto-Negotiation Advertisement Register
Table 30. Register 4: Auto-Negotiation Advertisement
Bit(s) Name Description Default R/W
15 14 13 12:5
Next Page Reserved Remote Fault Technology Ability Field Selector Field
Constant 0 = Transmitting primary capability data page This bit is reserved and should be set to 0b. 1 = Indicate link partner's remote fault 0 = No remote fault Technology Ability Field is an 8-bit field containing information indicating supported technologies specific to the selector field value. The Selector Field is a 5-bit field identifying the type of message to be sent via Auto-Negotiation. This field is read only in the 82551ER and contains a value of 00001b, IEEE Standard 802.3.
0 0 0 00101111
RO RO RW RW
4:0
00001
RO
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82551ER -- Networking Silicon
9.1.6
Register 5: Auto-Negotiation Link Partner Ability Register
Table 31. Auto-Negotiation Link Partner Ability
Bit(s) Name Description Default R/W
15 14
Next Page Acknowledge
This bit reflects the PHY's link partner's AutoNegotiation ability. This bit is used to indicate that the 82551ER's PHY unit has successfully received its link partner's AutoNegotiation advertising ability. This bit reflects the PHY's link partner's AutoNegotiation ability. This bit reflects the PHY's link partner's AutoNegotiation ability. This bit reflects the PHY's link partner's AutoNegotiation ability.
---
RO RO
13 12:5 4:0
Remote Fault Technology Ability Field Selector Field
----
RO RO RO
9.1.7
Register 6: Auto-Negotiation Expansion Register
Table 32. Register 6: Auto-Negotiation Expansion
Bit(s) Name Description Default R/W
15:5 4
Reserved Parallel Detection Fault
These bits are reserved and should be set to 0b. 1 = Fault detected via parallel detection (multiple link fault occurred) 0 = No fault detected via parallel detection This bit will self-clear on read
0 0
RO RO SC LH
3 2 1
Link Partner Next page Able Next Page Able Page Received
1 = Link Partner is Next Page able 0 = Link Partner is not Next Page able 1 = Local drive is Next Page able 0 = Local drive is not Next Page able 1 = New Page received 0 = New Page not received This bit will self-clear on read.
0 0 0
RO RO RO SC LH
0
Link Partner Auto- 1 = Link Partner is Auto-Negotiation able Negotiation Able 0 = Link Partner is not Auto-Negotiation able
0
RO
9.2
MDI Registers 8 - 15
Registers eight through fifteen are reserved for IEEE.
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Networking Silicon -- 82551ER
9.3
9.3.1
MDI Register 16 - 31
Register 16: PHY Unit Status and Control Register
Table 33. PHY Unit Status and Control
Bit(s) Name Description Default R/W
15:14 13
Reserved Carrier Sense Disconnect Control Transmit Flow Control Disable
These bits are reserved and should be set to 00b This bit enables the disconnect function. 1 = Disconnect function enabled 0 = Disconnect function disabled This bit enables Transmit Flow Control 1 = Transmit Flow Control enabled 0 = Transmit Flow Control disabled This bit indicates receipt status of the 100BASE-TX receive de-serializer in-sync. This bit indicates the power state of 100BASE-TX PHY unit. 1 = Power-Down 0 = Normal operation
00 0
RW RW
12
0
RW
11
Receive DeSerializer In-Sync Indication 100BASE-TX Power-Down
--
RO
10
1
RO
9
10BASE-T Power-Down
This bit indicates the power state of 100BASE-TX PHY unit. 1 = Power-Down 0 = Normal operation
1
RO
8
Polarity
This bit indicates 10BASE-T polarity. 1 = Reverse polarity 0 = Normal polarity
--
RO
7:2 1
Reserved Speed
These bits are reserved and should be set to 0B. This bit indicates the Auto-Negotiation result. 1 = 100 Mbps 0 = 10 Mbps
000000 --
RO RO
0
Duplex Mode
This bit indicates the Auto-Negotiation result. 1 = Full Duplex 0 = Half Duplex
--
RO
9.3.2
Register 17: PHY Unit Special Control Register
Table 34. Register 17: PHY Unit Special Control
Bit(s) Name Description Default R/W
15 14 13
Scrambler Bypass By-pass 4B/5B Force Transmit HPattern
1 = By-pass Scrambler 0 = Normal operations 1 = 4 bit to 5 bit by-pass 0 = Normal operation 1 = Force transmit H-pattern 0 = Normal operation
0 0 0
RW RW RW
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82551ER -- Networking Silicon
Table 34. Register 17: PHY Unit Special Control
Bit(s) Name Description Default R/W
12 11 10 9 8 7 6 5 4 3 2 1 0
Force 34 Transmit Pattern Good Link Reserved Transmit Carrier Sense Disable Disable Dynamic Power-Down Auto-Negotiation Loopback MDI Tri-State Filter By-pass Auto Polarity Disable Squelch Disable Extended Squelch Link Integrity Disable Jabber Function Disable
1 = Force 34 transmit pattern 0 = Normal operation 1 = 100BASE-TX link good 0 = Normal operation This bit is reserved and should be set to 0b. 1 = Transmit Carrier Sense disabled 0 = Transmit Carrier Sense enabled 1 = Dynamic Power-Down disabled 0 = Dynamic Power-Down enabled (normal) 1 = Auto-Negotiation loopback 0 = Auto-Negotiation normal mode 1 = MDI Tri-state (transmit driver tri-states) 0 = Normal operation 1 = By-pass filter 0 = Normal filter operation 1 = Auto Polarity disabled 0 = Normal polarity operation 1 = 10BASE-T squelch test disable 0 = Normal squelch operation 1 = 10BASE-T Extended Squelch control enabled 0 = 10BASE-T Extended Squelch control disabled 1 = Link disabled 0 = Normal Link Integrity operation 1 = Jabber disabled 0 = Normal Jabber operation
0 0 0 0 0 0 0 0 0 0 0 0 0
RW RW RW RW RW RW RW RW RW RW RW RW RW
9.3.3
Register 18: PHY Address Register
Table 35. Register 18: PHY Address
Bit(s) Name Description Default R/W
15:5 4:0
Reserved PHY Address
These bits are reserved and should be set to a constant `0' These bits are set to the PHY's address, 00001b.
0 1
RO RO
9.3.4
Register 19: 100BASE-TX Receive False Carrier Counter
Table 36. Register 19: 100BASE-TX Receive False Carrier Counter
Bit(s) Name Description Default R/W
15:0
Receive False Carrier
These bits are used for the false carrier counter.
--
RO SC
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Networking Silicon -- 82551ER
9.3.5
Register 20: 100BASE-TX Receive Disconnect Counter
Table 37. Register 20: 100BASE-TX Receive Disconnect Counter
Bit(s) Name Description Default R/W
15:0
Disconnect Event
This field contains a 16-bit counter that increments for each disconnect event. The counter freezes when full and self-clears on read
--
RO SC
9.3.6
Register 21: 100BASE-TX Receive Error Frame Counter
Table 38. Register 21: 100BASE-TX Receive Error Frame Counter
Bit(s) Name Description Default R/W
15:0
Receive Error Frame
This field contains a 16-bit counter that increments once per frame for any receive error condition (such as a symbol error or premature end of frame) in that frame. The counter freezes when full and self-clears on read.
--
RO SC
9.3.7
Register 22: Receive Symbol Error Counter
Table 39. Register 22: Receive Symbol Error Counter
Bit(s) Name Description Default R/W
15:0
Symbol Error Counter
This field contains a 16-bit counter that increments for each symbol error. The counter freezes when full and self-clears on read. In a frame with a bad symbol, each sequential six bad symbols count as one.
--
RO SC
9.3.8
Register 23: 100BASE-TX Receive Premature End of Frame Error Counter
Table 40. Register 23: 100BASE-TX Receive Premature End of Frame Error Counter
Bit(s) Name Description Default R/W
15:0
Premature End of Frame
This field contains a 16-bit counter that increments for each premature end of frame event. The counter freezes when full and self-clears on read.
--
RO SC
9.3.9
Register 24: 10BASE-T Receive End of Frame Error Counter
Table 41. Register 24: 10BASE-T Receive End of Frame Error Counter
Bit(s) Name Description Default R/W
15:0
End of Frame Counter
This is a 16-bit counter that increments for each end of frame error event. The counter freezes when full and self-clears on read.
--
RO SC
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82551ER -- Networking Silicon
9.3.10
Register 25: 10BASE-T Transmit Jabber Detect Counter
Table 42. Register 25: 10BASE-T Transmit Jabber Detect Counter
Bit(s) Name Description Default R/W
15:0
Jabber Detect Counter
This is a 16-bit counter that increments for each jabber detection event. The counter freezes when full and self-clears on read.
--
RO SC
9.3.11
Register 26: Equalizer Control and Status Register
Table 43. Register 26: Equalizer Control and Status
Bit(s) Name Description Default R/W
15:0
RFU
Reserved for Future Use
--
RW
9.3.12
Register 27: PHY Unit Special Control Register
Table 44. Register 27: PHY Unit Special Control
Bit(s) Name Description Default R/W
15:3 2:0
Reserved LED Switch Control
These bits are reserved and should be set to 0b. Value 000 001 010 011 100 101 110 111 ACTLED Activity Speed Speed Activity Off Off On On LILED Link Collision Link Collision Off On Off On
0 000
RW RW
9.3.13
Register 28: Reserved
This register is reserved and should not be used.
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9.3.14
Register 29: Hardware Integrity Control Register
Table 45. Register 29: Hardware Integrity Control
Bit(s) Name Description Default R/W
15
HWI Enable
This bit enables the HWI feature causing the PHY unit to enter HWI test mode. 1 = HWI enabled 0 = HWI disabled
0
RW
14
Ability Check
This bit reports the results of the HWI ability check and is valid 100 s after the HWI Enabled bit (bit 15 of this register) is set (1b). 1 = Test passed 0 = Test failed (HWI ability not detected)
RO
13
Test Execute
When this bit is set, the PHY unit launches test pulses on the wire to determine the distance to the cable's high or low impedance point. 1 = Execute test 0 = Do not execute test
WO
12:11 10:9
Reserved LowZ/HighZ
These bits are reserved and should be set to 0b. This field of bits indicates either a short (Low Z) or open (high Z) on the line. It is valid 100 s after the Test Execute bit (bit 13 of this register) is set. 1 = Short (low Z) 0 = Open (high Z)
00
RO RO
8:0
Distance
These bits define the distance to the short or open in the cable and are valid 100 s after the Test Execute bit (bit 13 of this register) is set. The distance is defined in granularities of 80 cm (35 inches).
RO
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82551ER -- Networking Silicon
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Networking Silicon -- 82551ER
10.0
Note:
Electrical and Timing Specifications
This section contains information on products in sampling and early production phase of development. Do not finalize a design with this information. Revised information will be published when the product becomes available.
10.1
Absolute Maximum Ratings
Maximum ratings are listed below: Case Temperature under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 85 C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 C to 140 C Outputs and Supply Voltages (except PCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 5.0 V PCI Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.50 V to 5.25 V Transmit Data Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 8.0 V Input Voltages (except PCI ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0 V to 5.0 V PCI Input Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V 6.0 V Stresses above the listed absolute maximum ratings may cause permanent damage to the 82551ER device. This is a stress rating only and functional operations of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
10.2
DC Specifications
Table 46. General DC Specifications
Symbol Parameter Condition Min Typical Max Units Notes
VCC VIO
Supply Voltage Periphery Clamp Voltage PCI
3.0 4.75
3.3 5.0
3.6 5.25
V V 1
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82551ER -- Networking Silicon
Table 46. General DC Specifications
D0a 10BASE-T full function Power Supply (10BASE-T) D1, D2, D3hot 10BASE-T wake-up enabled D3cold 10BASE-T wakeup ensabled D3cold 10BASE-T wakeup disabled ICC D0a 100BASE-TX full function Power Supply (100BASE-TX) D1, D2, D3hot 100BASETX wake-up enabled D3cold 100BASE-TX wake-up ensabled D3cold 100BASE-TX wake-up disabled 85 65 40 1.5 135 110 95 1.5 100 75 50 2.0 155 125 110 2.0 mA mA mA mA mA mA mA mA 2 2
NOTES: 1. VIO should be 5 V 5% in any PCI environment (either 5 V or 3.3 V signaling). 2. Typical current consumption is in nominal operating conditions (VCC = 3.3 V) and average link activity. Maximum current consumption is in maximum VCC and maximum link activity.
The 82551ER supports PCI interface standards. In the PCI mode, it is five volts tolerant and supports both 5 V and 3.3 V signaling environments. Table 47. PCI Interface DC Specifications
Symbol Parameter Condition Min Max Units Notes
VIHP VILP VIPUP VIPDP IILP VOHP
Input High Voltage Input Low Voltage Input Pull-up Voltage Input Pull-down Voltage Input Leakage Current Output High Voltage 0 < VIN < VCC Iout = -2 mA Iout = -500 A Iout = 3 mA, 6 mA
0.475VCC -0.5 0.7VCC
VIO + 0.5 0.325VCC
V V V 1 1 2 PCI
0.2VCC 10 2.4 0.9VCC 0.55 0.1VCC 10 5 12 8 20 VO < VIO 1
V A V V V V pF pF pF nH mA
3, PCI
VOLP CINP CCLKP CIDSEL LPINP IOFFPME
Output Low Voltage Input Pin Capacitance CLK Pin Capacitance IDSEL Pin Capacitance Pin Inductance PME# Input Leakage Current
Iout = 1500 A
4 4 4 4 5
NOTES: 1. These values are only applicable in 3.3 V signaling environments. Outside of this limit the input buffer must consume its minimum current.
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2. Input leakage currents include high-Z output leakage for all bidirectional buffers with tristate outputs. 3. Signals without pull-up resistors have 3 mA low output current; and signals requiring pull-up resistors, 6 mA. The signals requiring pull-up resistors include: FRAME#, TRDY#, IRDY#, DEVSEL#, STOP#, SERR# and PERR#. 4. This value is characterized but not tested. 5. This input leakage current is the maximum allowable leakage into the PME# open drain driver when power is removed from VCC of the component. This assumes that no event has occurred to cause the device to assertion of PME#.
Table 48. Flash/EEPROM Interface DC Specifications
Symbol Parameter Condition Min Max Units Notes
VIHL VILL IILL VOHL VOLL CINL
Input High Voltage Input Low Voltage Input Low Leakage Current Output High Voltage Output Low Voltage Input Pin Capacitance 0 < VIN < VCC Iout = -1 mA Iout = 2 mA
2.0 -0.5
VCC + 0.5 0.8 20
V V A V
2.4 0.4 10
V pF 1
NOTE: 1. This value is characterized but not tested.
Table 49. LED Voltage/Current Characteristics
Symbol Parameter Condition Min Typical Max Units Notes
VOHLED VOLLED
Output High Voltage Output Low Voltage
Iout = -10 mA Iout = 10 mA
2.4 0.7
V V
Table 50. 100BASE-TX Voltage/Current Characteristics
Symbol Parameter Condition Min Typical Max Units Notes
RID100 VIDA100 VIDR100 VICM100 VOD100 ICCT100
Input Differential Impedance Input Differential Accept Peak Voltage Input Differential Reject Peak Voltage Input Common Mode Voltage Output Differential Peak Voltage Line Driver Supply Peak Current
DC
10 500 100 VCC/2 0.95 1.00 20 1.05
K mV mV V V mA 1, 2
RBIAS100 = 619
NOTES: 1. Current is measured on all VCC pins (VCC = 3.3 V).
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82551ER -- Networking Silicon
2. Transmitter peak current is attained by dividing the measured maximum differential output peak voltage by the load resistance value.
Figure 19. RBIAS100 Resistance Versus Transmitter Current
Rbias100
585 0hm
619 Ohm
650 Ohm 19mA 20 mA 21mA
Icct100
Table 51. 10BASE-T Voltage/Current Characteristics
Symbol Parameter Condition Min Typical Max Units Notes
RID10 VIDA10 VIDR10 VICM10 VOD10 ICCT10
Input Differential Impedance Input Differential Accept Peak Voltage Input Differential Reject Peak Voltage Input Common Mode Voltage Output Differential Peak Voltage Line Driver Supply Peak Current
10 MHz 5 MHz f 10 MHz 5 MHz f 10 MHz
10 585 0 440 440 VCC/2 3100 300
K mV mV V 2.8 50 V mA 1, 2
RL = 100 RBIAS10 = 549
2.2
NOTES: 1. Current is measured on all VCC pins (VCC = 3.3 V). 2. Transmitter peak current is attained by dividing the measured maximum differential output peak voltage by the load resistance value.
Figure 20. RBIAS10 Resistance Versus Transmitter Current
Rbias10
621.5 0hm
549 Ohm
576 Ohm 19mA 20 mA 21mA
Icct10
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Networking Silicon -- 82551ER
10.3
AC Specifications
Table 52. AC Specifications for PCI Signaling
Symbol Parameter Condition Min Max Units Notes
Switching IOH(AC) Current High (Test Point) Switching IOL(AC) Current Low (Test Point) ICL ICH slewRP slewFP Low Clamp Current High Clamp Current
0 < VOUT 1.4 1.4 < VOUT < 0.9VCC 0.7VCC < VOUT < VCC VOUT = 0.7VCC VOUT 2.2 2.2 > VOUT > 0.1VCC 0.18VCC > VOUT > 0 VOUT = 0.18VCC -3 < VIN -1 VCC + 4 > VIN VCC + 1
-44 -17.1(VCC - VOUT) Eqn A -32VCC 95 VOUT/0.023 Eqn B 38VCC -25 + (VIN + 1)/0.015 25 + (VIN - VCC -1)/ 0.015 1 1 4 4
mA mA mA mA mA mA mA mA mA mA V/ns V/ns
1 1 2 2 1 1 2 2 3 3
PCI Output Rise 0.4 V to 2.4 V Slew Rate PCI Output Fall Slew Rate 2.4 V to 0.4 V
NOTES: 1. Switching Current High specifications are not relevant to PME#, SERR#, or INTA#, which are open drain outputs. 2. Maximum current requirements will be met as drivers pull beyond the first step voltage (AC drive point). Equations defining these maximums (A and B) are provided. To facilitate component testing, a maximum current test point is defined for each side of the output driver.
Equation A. Equation B.
IOH = (98/VCC)*(Vout - VCC)*(Vout + 0.4VCC), for VCC > Vout > 0.7VCC IOL = (256/VCC)*(Vout)*(VCC - Vout), for 0 < Vout < 0.18VCC
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82551ER -- Networking Silicon
10.4
10.4.1
10.4.1.1
Timing Specifications
Clocks Specifications
PCI Clock Specifications
The 82551ER uses the PCI Clock signal directly. Figure 21 shows the clock waveform and required measurement points for the PCI Clock signal. Table 53 summarizes the PCI Clock specifications.
Figure 21. PCI Clock Waveform
0.6VCC 0.475VCC 0.4VCC 0.325V CC 0.2VCC 0.4VCC p-to-p (minimum)
T_high T_cyc
T_low
Table 53. PCI Clock Specifications
Symbol Parameter Min Max Units Notes
T1 T2 T3 T4
Tcyc Thigh Tlow Tslew
CLK Cycle Time CLK High Time CLK Low Time CLK Slew Rate
30 11 11 1 4
ns ns ns V/ns
1
2
NOTES: 1. The 82551ER will work with any PCI clock frequency up to 33 MHz. 2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate is met across the minimum peak-to-peak portion of the clock waveform as shown in Figure 21.
10.4.1.2
X1 Specifications
X1 serves as a signal input from an external crystal or oscillator. Table 54 defines the 82551ER requirements from this signal.
Table 54. X1 Clock Specifications
Symbol Parameter Min Typical Max Units Notes
T8 T9
Tx1_dc Tx1_pr
X1 Duty Cycle X1 Period
40% 40
60% ns 50PPM
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Networking Silicon -- 82551ER
10.4.2
10.4.2.1
Timing Parameters
Measurement and Test Conditions
Figure 22, Figure 23, and Table 55 define the conditions under which timing measurements are done. The component test guarantees that all timings are met with minimum clock slew rate (slowest edge) and voltage swing. The design must guarantee that minimum timings are also met with maximum clock slew rate (fastest edge) and voltage swing. In addition, the design must guarantee proper input operation for input voltage swings and slew rates that exceed the specified test conditions.
Figure 22. Output Timing Measurement Conditions
V_th
CLK
V_test V_tl T_val
OUTPUT DELAY
V_step
Tri-State OUTPUT
V_test
V_test
T_on T_off
Figure 23. Input Timing Measurement Conditions
V_th
CLK
T_su
V_test V_tl T_h V_th
INPUT
V_tl
V_test
inputs valid
V_test
V_max
Table 55. Measure and Test Condition Parameters
Symbol PCI Level CardBus Level Units Notes
Vth Vtl
0.6VCC 0.2VCC
0.6VCC 0.2VCC
V V
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82551ER -- Networking Silicon
Table 55. Measure and Test Condition Parameters
Vtest Vstep (rising edge) 0.4VCC 0.285VCC 0.4VCC 0.325VCC 0.475VCC 0.475VCC 0.325VCC 0.4VCC 1 V V V V V V V/ns Min Delay Max Delay Min Delay Max Delay
Vstep (falling edge) Vmax Input Signal Edge Rate
0.615VCC 0.4VCC 1
NOTE: Input test is done with 0.1VCC overdrive. Vmax specifies the maximum peak-to-peak waveform allowed for testing input timing.
Table 56. Measure and Test Condition Parameters
Symbol PCI Level Units Notes
Vth Vtl Vtest Vstep (rising edge)
0.6VCC 0.2VCC 0.4VCC 0.285VCC
V V V V V V Min Delay Max Delay Min Delay Max Delay
Vstep (falling edge) Vmax Input Signal Edge Rate
0.615VCC 0.4VCC 1
V V V/ns
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10.4.2.2
PCI Timings
Table 57. PCI Timing Parameters
Symbol Parameter Min Max Units Notes
T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
tval tval(ptp) ton toff tsu tsu(ptp) th trst Trst-clk Trst-off
PCI CLK to Signal Valid Delay PCI CLK to Signal Valid Delay (pointto-point) Float to Active Delay Active to Float Delay Input Setup Time to CLK PCI Input Setup Time to CLK (point-topoint) Input Hold Time from CLK Reset Active Time After Power Stable PCI Reset Active Time After CLK Stable Reset Active to Output Float Delay
2 2 2
11 12
ns ns ns
1, 2, 3 1, 2, 3 1 1 3, 4 3, 4 5 5 5 5, 6
28 7 10 0 1 100 40
ns ns ns ns ms clocks ns
NOTES: 1. Timing measurement conditions are illustrated in Figure 22. 2. PCI minimum times are specified with loads as detailed in the PCI Bus Specification, Revision 2.1, Section 4.2.3.2. 3. n a PCI environment, REQ# and GNT# are point-to-point signals and have different output valid delay times and input setup times than bussed signals. All other signals are bussed. 4. Timing measurement conditions are illustrated in Figure 23. 5. RST# is asserted and de-asserted asynchronously with respect to the CLK signal. 6. All PCI interface output drivers are floated when RST# is active.
10.4.2.3
Flash Interface Timings
The 82551ER is designed to support up to 150 ns of Flash access time. The VPP signal in the Flash implementation should be connected permanently to 12 V. Thus, writing to the Flash is controlled only by the FLWE# pin. Table 58 provides the timing parameters for the Flash interface signals. The timing parameters are illustrated in Figure 24 and Figure 25.
Table 58. Flash Timing Parameters
Symbol Parameter Min Max Units Notes
T35 T36 T37 T38
tflrwc tflacc tflce tfloe
Flash Read/Write Cycle Time FLA to Read FLD Setup Time FLCS# to Read FLD Setup Time FLOE# Active to Read FLD Setup Time
150 150 150 120
ns ns ns ns
1, Flash tAVAV = 150 ns 1, Flash tAVQV = 150 ns 1, Flash tELQV = 150 ns 1, Flash tGLQV = 55 ns
Datasheet
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82551ER -- Networking Silicon
Table 58. Flash Timing Parameters
T39 T40 T41 T42 T43 T44 T45 T46 T47 T48 T49 tfldf tflas tflah tflcs tflch tflds tfldh tflwp tflwph tMioha tMiohi FLOE# Inactive to FLD Driven Delay Time FLA Setup Time before FLWE# FLA Hold Time after FLWE# FLCS# Hold Time before FLWE# FLCS# Hold Time after FLWE# FLD Setup Time FLD Hold Time Write Pulse Width Write Pulse Width High IOCHRDY Hold Time after FLWE# or FLOE# Active IOCHRDY Hold Time after FLWE# or FLOE# Inactive 0 50 5 200 30 30 150 10 120 25 25 ns ns ns ns ns ns ns ns ns ns ns 1, Flash tGHQZ = 35 ns 2, Flash tAVWL = 0 ns 2, Flash tWLAX = 60 ns 2, Flash tELWL = 20 ns 2, Flash tWHEH = 0 ns 2, Flash tDVWH = 50 ns 2, Flash tWHDX = 10 ns 2, Flash tWLWH = 60 ns 2, Flash tWHWL = 20 ns
NOTES: 1. These timing specifications apply to Flash read cycles. The Flash timings referenced are 28F020-150 timings. 2. These timing specifications apply to Flash write cycles. The Flash timings referenced are 28F020-150 timings.
Figure 24. Flash Timings for a Read Cycle
FLADDR
Address Stable
T35
FLCS#
T37
FLOE#
T38 T36 T39
FLDATA-R
T49
Data In
T48
IOCHRDY
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Datasheet
Networking Silicon -- 82551ER
Figure 25. Flash Timings for a Write Cycle
T35
FLADDR
Address Stable
T40 T41
FLCS#
T42 T46 T43
FLWE#
T47 T44 T45
FLDATA-W
T49
Data Out
T48
IOCHRDY
10.4.2.4
EEPROM Interface Timings
The 82551ER is designed to support a standard 64x16 or 256x16 serial EEPROM. Table 59 provides the timing parameters for the EEPROM interface signals. The timing parameters are illustrated in Figure 26.
Table 59. EEPROM Timing Parameters
Symbol Parameter Min Max Units Notes
T51 T52 T53 T54 T55
tECSS tECSH tEDIS tEDIH tECS
Delay from EECS High to EESK High Delay from EESK Low to EECS Low Setup Time of EEDI to EESK Hold Time of EEDI after EESK EECS Low Time
300 30 300 300 750
ns ns ns ns ns
EEPROM tcss = 50 ns EEPROM tcsh = 0 ns EEPROM tdis = 150 ns EEPROM tdih = 150 ms EEPROM tcs = 250 ns
Datasheet
79
82551ER -- Networking Silicon
Figure 26. EEPROM Timings
EECS
T51 T52
FLA15EESK
T53 T54
FLA13EEDI
10.4.2.5
PHY Timings
Table 60. 10BASE-T Normal Link Pulse (NLP) Timing Parameters
Symbol Parameter Condition Min Typ Max Units
T56 T57
Tnlp_wid Tnlp_per
NLP Width NLP Period
10 Mbps 10 Mbps 8
100 24
ns ms
Figure 27. 10BASE-T Normal Link Pulse (NLP) Timings
T57 T56
Normal Link Pulse
Table 61. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters
Symbol Parameter Min Typ Max Units
T58 T59 T60 T61 T62 T63
Tflp_wid Tflp_clk_clk Tflp_clk_dat
FLP Width (clock/data) Clock Pulse to Clock Pulse Period Clock Pulse to Data Pulse Period 111 55.5 17
100 125 62.5 139 69.5 33 2 8 24
ns s s
Tflp_bur_num Number of Pulses in one burst Tflp_bur_wid Tflp_bur_per FLP Burst Width FLP Burst Period
ms ms
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Datasheet
Networking Silicon -- 82551ER
Figure 28. Auto-Negotiation Fast Link Pulse (FLP) Timings
T59 T60 T58 Fast Link Pulse Clock Pulse T62 FLP Bursts Data Pulse Clock Pulse
T63
Table 62. 100Base-TX Transmitter AC Specification
Symbol Parameter Condition Min Typ Max Units
T64
Tjit
TDP/TDN Differential Output Peak Jitter
HLS Data
1400
ps
Datasheet
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82551ER -- Networking Silicon
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Datasheet
Networking Silicon -- 82551ER
11.0
11.1
Package and Pinout Information
Package Information
The 82551ER is a 196-pin Ball Grid Array (BGA) package. Package dimensions are shown in Figure 29. More information on Intel(R) device packaging is available in the Intel Packaging Handbook.
Figure 29. Dimension Diagram for the 196-pin BGA
NOTE: All dimensions are in millimeters.
Datasheet
83
82551ER -- Networking Silicon
11.2
11.2.1
Pinout Information
Pin Assignments
Table 63. Pin Assignments
Pin Name Pin Name Pin Name
A1 A4 A7 A10 A13 B1 B4 B7 B10 B13 C1 C4 C7 C10 C13 D1 D4 D7 D10 D13 E1 E4 E7 E10 E13 F1 F4 F7 F10 F13 G1 G4 G7 G10
NC IDSEL VCC NC TEST AD22 AD24 VSSPP NC RBIAS100 AD21 C/BE3# AD29 VSSPT TDP AD18 VSS VSS NC TEXEC VCC VSS VSS VSS RDP IRDY# VSS VSS VSS FLD1 CLK NC VSS VSS
A2 A5 A8 A11 A14 B2 B5 B8 B11 B14 C2 C5 C8 C11 C14 D2 D5 D8 D11 D14 E2 E5 E8 E11 E14 F2 F5 F8 F11 F14 G2 G5 G8 G11
SERR# AD25 AD30 VCC NC AD23 AD26 AD31 SPEEDLED RBIAS10 RST# NC CLKRUN# ACTLED TDN AD19 VSS VSS NC TCK VSSPP VSS VSS NC RDN FRAME# VSS VSS VSS FLD0 VIO VCC VSS VSS
A3 A6 A9 A12
VCC PME# ALTRST# LILED
B3 B6 B9 B12
VSSPP AD27 ISOLATE# TO
C3 C6 C9 C12
REQ# AD28 NC VREF
D3 D6 D9 D12
AD20 VSS NC TI
E3 E6 E9 E12
AD17 VSS VSS VCC
F3 F6 F9 F12
C/BE2# VSS VSS FLD2
G3 G6 G9 G12
TRDY# VCC VSS FLD3
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Datasheet
Networking Silicon -- 82551ER
Table 63. Pin Assignments
Pin Name Pin Name Pin Name
G13 H1 H4 H7 H10 H13 J1 J4 J7 J10 J13 K1 K4 K7 K10 K13 L1 L4 L7 L10 L13 M1 M4 M7 M10 M13 N1 N4 N7 N10 N13 P1 P4 P7 P10 P13
VCC STOP# NC VCC VSS FLD5 PAR NC VCC VCCR FLA0 AD16 VCC VCC VCC VCC AD14 VCC NC VCC FLA4 AD11 C/BE0# AD1 FLA15/EESK FLA7 VSSPP AD7 AD0 FLA14/EEDO FLA10 NC AD6 EECS FLA13/EEDI FLA9
G14 H2 H5 H8 H11 H14 J2 J5 J8 J11 J14 K2 K5 K8 K11 K14 L2 L5 L8 L11 L14 M2 M5 M8 M11 M14 N2 N5 N8 N11 N14 P2 P5 P8 P11 P14
VSSPL INTA# VCC VCC NC FLD4 PERR# VCC VCC VCCR FLD7 VSSPP VCC VCC VCC FLA2 AD15 VCC NC VSS FLA3 AD12 AD5 FLOE# FLA12 FLA6 AD10 AD4 VCC X1 FLA8 VCC AD3 VSSPL X2 NC P3 P6 P9 P12 AD8 AD2 FLA16 VCC N3 N6 N9 N12 AD9 VCC FLCS# VSSPL M3 M6 M9 M12 AD13 VSSPP FLWE# FLA11 L3 L6 L9 L12 C/BE#1 VSS VCC FLA5 K3 K6 K9 K12 VCC VCC VCC VSSPL J3 J6 J9 J12 GNT# VCC VCC FLA1 H3 H6 H9 H12 DEVSEL# VCC VSS FLD6
Datasheet
85
82551ER -- Networking Silicon
11.2.2
Ball Grid Array Diagram
Figure 30. Ball Grid Array Diagram
1 A B C D E F G H J K L M N P
NC
2
SER R#
3
VCC
4
IDSE L
5
AD25
6
PME #
7
VCC
8
AD3 0
9
ALT RST # ISOL ATE #
10
NC
11
VCC
12
LILE D
13
TES T RBI AS1 00
14
NC
AD2 2
AD2 3
VSS PP
AD2 4
AD2 6
AD2 7
VSS PP
AD3 1 CLK RUN #
NC
SPE EDL ED ACT LED
TO
RBI AS1 0
AD2 1
RST #
REQ #
CBE 3#
NC
AD2 8
AD2 9
NC
VSS PT
VRE F
TDP
TDN
AD1 8
AD1 9
AD2 0
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
TI
TEX EC
TCK
VCC
VSS PP
AD1 7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
VCC
RDP
RDN
IRD Y#
FRA ME#
CBE 2#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
FLD 2
FLD 1
FLD 0
CLK
VIO
TRD Y# DEV SEL # GNT #
NC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
FLD 13
VCC
VSS PL
82551ER Ballout
STO P# INT A# NC VCC VCC
BGA 196 (15mm x 15mm)
VCC VCC VSS VSS NC
(top view)
FLD 6 FLD 5 FLD 4
PAR
PER R#
NC
VCC
VCC
VCC
VCC
VCC
VCC R
VCC R
FLA 1
FLA 0
FLD 7
AD1 6
VSS PP
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS PL
VCC
FLA 2
AD1 4
AD1 5
CBE 1#
VCC
VCC
VSS
MD MCS #
NC
VCC
VCC
VSS
FLA 5
FLA 4
FLA 3
AD1 1
AD1 2
AD1 3
CBE 0#
AD5
VSS PP
AD1
FLO E#
FLW E#
FL 1 A 5 / ES EK FL 1 A 4 / ED E O FL 1 A 3 / E DI E
FLA 12
FLA 11
FLA 7
FLA 6
VSS PP
AD1 0
AD9
AD7
AD4
VCC
AD0
VCC
FLC S#
X1
VSS PL
FLA 10
FLA 8
NC
VCC
AD8
AD6
AD3
AD2
EEC S
VSS PL
FLA 16
X2
VCC
FLA 9
NC
86
Datasheet

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